PC87373 datasheet(53/174 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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Revision 1.1

3.9.3

Parallel Port Standard Configuration Register

This register is reset to F2h.

Power Well: VDD3

Location:

Index F0h

Type:

R/W

Bit

76543210

Name

Parallel Port Mode Select

Extended

Access

Reserved

Power

Mode

Control

TRI-STATE

Control

Reset

11110010

Bit

Description

7-5

Parallel Port Mode Select. The mode selected by writing to these bits, is reﬂected by bits 3-0 in the Parallel

Port Modiﬁed Conﬁguration Register (see Section 3.9.4 on page 54).

Bits

7 6 5

Mode

0 0 0:

SPP-Compatible mode. PD7-0 are always output signals

0 0 1:

SPP Extended mode. PD7-0 direction is controlled by software

0 1 0:

EPP 1.7 mode

0 1 1:

EPP 1.9 mode

1 0 0:

ECP mode (IEEE1284 register set), with no support for EPP mode

1 0 1:

Reserved

1 1 0:

Reserved

1 1 1:

ECP mode (IEEE1284 register set), with EPP mode selectable as mode “100” (default)

Selection of EPP 1.7 or 1.9 in ECP mode “100” is controlled by bit 4 of the Control2 conﬁguration register of

the Parallel Port at offset 02h.

Note: Before setting bits 7-5, enable the Parallel Port and set CTR/DCR (at base address + 2) to C4h.

Extended Register Access.

0: Registers at base (address) + 403h, base + 404h and base + 405h are not accessible (reads and writes are

ignored)

1: Registers at base (address) + 403h, base + 404h and base + 405h are accessible. This option supports runtime

configuration within the Parallel Port address space (default).

3-2

Reserved.

Power Mode Control. When the logical device is active:

0: Parallel Port clock disabled. ECP modes and EPP time-out are not functional when the logical device is active.

Registers are maintained.

1: Parallel Port clock enabled. All operation modes are functional when the logical device is active (default).

TRI-STATE Control. When this bit is set to 1 and the logical device is inactive, the logical device output pins

are in TRI-STATE (see Section 3.3.2 on page 41).

0: Normal outputs (default)

1: TRI-STATE outputs when the logical device is inactive

PC87373 数据表(PDF) 53 Page - National Semiconductor (TI)

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PC87373 数据表(PDF) 53 Page - National Semiconductor (TI)

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