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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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PC87373 数据表(PDF) 77 Page - National Semiconductor (TI) |
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PC87373 数据表(HTML) 77 Page - National Semiconductor (TI) |
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77 / 174 page  5.0 General-Purpose Input/Output (GPIO) Ports (Continued) 77 www.national.com Revision 1.1 5.4 GPIO PORT REGISTERS The following abbreviations are used to indicate the Register Type: q R/W = Read/Write. q R = Read from register (data written to this address is sent to a different register). q W = Write (see above). q RO = Read Only. q WO = Write Only. Reading from the bit returns 0. q R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. q R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect. 5.4.1 GPIO Pin Configuration Registers Structure For each GPIO Port, there is a group of eight identical sets of configuration registers. Each set is associated with one GPIO pin. The entire group is mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register (see Section 3.14.3 on page 64), which functions as an index register for the pin, and the selected GPCFG1, GPEVR and GPCFG2 registers, which reflect the configuration of the currently selected pin (see Table 29). All of these registers are VSB3 powered. 5.4.2 GPIO Port Runtime Register Map All of these registers are VSB3 powered. Table 29. GPIO Configuration Registers Index Configuration Register or Action Type Power Well Reset F0h GPIO Pin Select register (GPSEL) R/W VSB3 00h F1h GPIO Pin Configuration register 1 (GPCFG1) Varies per bit VSB3 40h F2h GPIO Pin Event Routing register (GPEVR) R/W or RO VSB3 01h F3h GPIO Pin Configuration register 2 (GPCFG2) R/W or RO VSB3 00h F8h GPIO Mode Select register (GPMODE) R/W or RO VSB3 01h Table 30. GPIO Port Runtime Register Map Offset Mnemonic Register Name Type Power Well Reset Section SEPDIO1 =1 1. See Section 3.14.7 on page 66 SEPDIO = 0 Device specific2 2. The location of this register is defined in Section 3.14.1 on page 62. GPDO GPIO Data Out R/W RO VSB3 FFh 5.4.3 Device specific2 GPDI GPIO Data In RO RO VSB3 − 5.4.4 Device specific2 GPEVEN GPIO Event Enable R/W RO VSB3 00h 5.4.5 Device specific2 GPEVST GPIO Event Status R/W1C RO VSB3 00h 5.4.6 Device specific2 GPDIO GPIO Data In/Out R/W R/W VSB3 FFh3 3. The data read from this register after reset is undefined. 5.4.7 |
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