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PC87373 数据表(PDF) 62 Page - National Semiconductor (TI) |
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PC87373 数据表(HTML) 62 Page - National Semiconductor (TI) |
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62 / 174 page  3.0 Device Architecture and Configuration (Continued) 62 www.national.com Revision 1.1 3.14 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION 3.14.1 General Description The GPIO functional block includes 13 pins arranged in two ports: q Port 0 contains eight GPIOE pins (i.e., GPIO pins with event detection). q Port 1 contains four GPIOE pins and one GPIO pin. The pins of Ports 0 and 1 have full event detection capability (see Section 1.3 on page 15), enabling them to trigger an IRQ. In addition, through the SWC functional block, the pins of Ports 0 and 1 can trigger the SIOPME signal. An exception is the GPIO14 pin of Port 1, which has no event detection and therefore cannot trigger IRQ or SIOPME. All 13 GPIO pins are powered from the VSB3 well. The 10 runtime registers associated with the two ports are arranged in the GPIO address space as shown in Table 23. Each GPIO port with wake-up event detection capability has five runtime registers. The GPIO base address is 32-byte aligned. Address bits 4-0 are used to indicate the register offset. The specific runtime registers implemented in the PC87373 devices are shown in Table 23. All of these registers are VSB3 powered. Table 23. Runtime Registers in GPIO Address Space Offset Mnemonic Register Name Port Power Well Type SEPDIO1 =1 1. See Section 3.14.7 on page 66 SEPDIO = 0 00h GPDO0 GPIO Data Out 0 0 VSB3 R/W RO 01h GPDI0 GPIO Data In 0 VSB3 RO RO 02h GPEVEN0 GPIO Event Enable 0 VSB3 R/W RO 03h GPEVST0 GPIO Event Status 0 VSB3 R/W1C RO 04h GPDO1 GPIO Data Out 1 1 VSB3 R/W RO 05h GPDI1 GPIO Data In 1 VSB3 RO RO 06h GPEVEN1 GPIO Event Enable 1 VSB3 R/W RO 07h GPEVST1 GPIO Event Status 1 VSB3 R/W1C RO 15h GPDIO0 GPIO Data In/Out 0 0 VSB3 R/W R/W 16h GPDIO1 GPIO Data In/Out 1 1 VSB3 R/W R/W |
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