PC87373 datasheet(31/174 Pages) NSC

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2.0 Power, Reset and Clocks (Continued)

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Revision 1.1

2.2.5

Software Reset

The Software reset is triggered by the host setting SWRST bit in SIOCF1 register (see Section 3.7.2 on page 44) via the

LPC interface. The Host Software reset performs the following actions:

• Loads default values to the V

DD3-powered unlocked bits in the Configuration Control.

• Loads default values to the V

SB3-powered unlocked GPIO Configuration and Data bits for those GPIO ports with

VDDLOAD = 1. VDDLOAD bit is not affected.

• Resets all the V

DD3-powered Legacy logical devices.

• Loads default values to all the V

DD3-powered Legacy module registers.

2.3 CLOCK DOMAINS

The PC87373 device has three clock domains, as shown in Table 6.

The LPC and 48 MHz clock domains, and the modules using them, are supplied by the Main power plane. Therefore, these

two clock domains are active only when the VDD3 power supply is on.

2.3.1

LPC Domain

The LPC clock signal at the PCI_CLK pin must become valid (to the extent specified in PCI_CLK and PCI_RESET on page

163) before the end of the VDD Power-Up reset (see Section 2.2.3).

2.3.2

48 MHz Domain

The 48 MHz clock domain is sourced by the on-chip Clock Generator (supplied by the Main power plane).

Following a VDD Power-Up reset, the software waits a period of t14MW +t14MVAL until a valid 14.31818 MHz clock signal is

available at the CLOCKI14 pin. Then, the software can set the HFCGEN bit in the CLOCKCF register to 1. This bit enables

the operation of the Clock Generator.

After the Clock Generator is enabled for operation, its output clock is frozen to a low level until the generator provides an

internal clock signal that meets all requirements. When the requirements are met, the 48 MHz clock domain starts toggling.

The status of the Clock Generator output clock is indicated by CKVALID bit in CLOCKCF register. While the Clock Generator

is stabilizing, this bit is 0, indicating a 48 MHz clock domain frozen at low level. After t48MD, the 48 MHz clock domain starts

toggling and this bit is set to 1. The software must wait for CKVALID bit to be set before it enables the FSCM or the Legacy

functions (Serial Ports, Parallel Port, FDC, KBC, MIDI, Game Port).

The on-chip Clock Generator multiplies the frequency of the clock signal (received through the CLOCKI14 pin) by a constant

value to obtain the 48 MHz output frequency.

Figure 3 shows a simplified diagram of the 32 KHz and the 48 MHz clock domains.

Table 6. Clock Domains of the PC87373

Clock

Domain

Frequency

Power

Plane

Source

Usage

LPC

Up to 33 MHz

VDD3

LPC clock input (PCI_CLK)

LPC bus Interface and Conﬁguration Registers

48 MHz

VDD3

On-chip Clock Generator

Legacy functions (Serial Ports, Parallel Port,

FDC, KBC, MIDI, Game Port) and FSCM

32 KHz

32.768 KHz

VSB3

Clock input (CLOCKI32)

SWC, GPIO and Glue Functions

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