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PC87373 数据表(PDF) 69 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 PC87373
功能描述  LPC SuperI/O with Glue Functions
PDF  174 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

PC87373 数据表(HTML) 69 Page - National Semiconductor (TI)

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3.0 Device Architecture and Configuration (Continued)
69
www.national.com
Revision 1.1
3.15.4 Fan Speed Control and Monitor Configuration Register 2 (FSCMCF2)
This register is reset by hardware to 00h.
Power Well: VDD3
Location:
Index F1h
Type:
Varies per bit
1
R/W or
RO
FANMON_EN1 (Fan Monitor Enable 1). When this bit is set to 1, the Fan Speed Monitor 1 is enabled
and the rate of pulses received at the FANTACH1 tachometer input is measured.
0: Disabled (default)
1: Enabled
0
R/W or
RO
TRI-STATE Control. When this bit is set to 1 and the logical device is inactive, the logical device output
pins are in TRI-STATE (see Section 3.3.2 on page 41).
0: Normal outputs (default)
1: TRI-STATE outputs when the logical device is inactive
Bit
76543210
Name
Reserved
FANCTL
_INV3
FANCTL
_EN3
FANMON
_EN3
Reserved
Reset
00000000
Bit
Type
Description
7-4
-
Reserved.
3
R/W or
RO
FANCTL_INV3 (Fan Control Output Invert 3). When this bit is set to 1, the signal at the FANPWM3
control output is inverted (pin GPIOE5/FANPWM3).
0: Normal signal at FANPWM3 (default)
1: Inverted signal at FANPWM3
2
R/W or
RO
FANCTL_EN3 (Fan Control Enable 3). When this bit is set to 1, the Fan Speed Controller 3 is enabled
and a PWM signal is generated at the FANPWM3 control output (pin GPIOE5/FANPWM3).
0: Disabled (default)
1: Enabled
1
R/W or
RO
FANMON_EN3 (Fan Monitor Enable 3). When this bit is set to 1, the Fan Speed Monitor 3 is enabled
and the rate of pulses, received at the FANTACH3 tachometer input, is measured.
0: Disabled (default)
1: Enabled
0-
Reserved.
Bit
Type
Description



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