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PC87373 数据表(PDF) 67 Page - National Semiconductor (TI) |
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PC87373 数据表(HTML) 67 Page - National Semiconductor (TI) |
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67 / 174 page  3.0 Device Architecture and Configuration (Continued) 67 www.national.com Revision 1.1 3.15 FAN SPEED CONTROL AND MONITOR (FSCM) CONFIGURATION 3.15.1 General Description This module includes three Fan Speed Control units (see Section 7 on page 107) and three Fan Speed Monitor units (see Section 8 on page 110). The 21 runtime registers of the six functional blocks are arranged in the address space shown in Table 25. The base address is 32-byte aligned. Address bits 0 −4 are used to indicate the register offset. 3.15.2 Logical Device 9 (FSCM) Configuration Table 26 lists the configuration registers that affect the Fan Speed Control and Monitor. Only the last registers (F0h and F1h) are described here. See Section 3.2.3 on page 36 for a detailed description of the other registers. Table 25. Runtime Registers in FSCM Address Space Offset Mnemonic Register Name Function 00h FMTHRL1 Fan Monitor 1 Threshold Low Fan Speed Monitor 1 01h FMTHRH1 Fan Monitor 1 Threshold High 02h FMSPRL1 Fan Monitor 1 Speed Low 03h FMSPRH1 Fan Monitor 1 Speed High 04h FMCSR1 Fan Monitor 1 Control & Status 05h FMTHRL2 Fan Monitor 2 Threshold Low Fan Speed Monitor 2 06h FMTHRH2 Fan Monitor 2 Threshold High 07h FMSPRL2 Fan Monitor 2 Speed Low 08h FMSPRH2 Fan Monitor 2 Speed High 09h FMCSR2 Fan Monitor 2 Control & Status 0Ah FMTHRL3 Fan Monitor 3 Threshold Low Fan Speed Monitor 3 0Bh FMTHRH3 Fan Monitor 3 Threshold High 0Ch FMSPRL3 Fan Monitor 3 Speed Low 0Dh FMSPRH3 Fan Monitor 3 Speed High 0Eh FMCSR3 Fan Monitor 3 Control & Status 0Fh Reserved 10h FCPSR1 Fan Control 1 Pre-Scale Fan Speed Control 1 11h FCDCR1 Fan Control 1 Duty Cycle 12h FCPSR2 Fan Control 2 Pre-Scale Fan Speed Control 2 13h FCDCR2 Fan Control 2 Duty Cycle 14h FCPSR3 Fan Control 3 Pre-Scale Fan Speed Control 3 15h FCDCR3 Fan Control 3 Duty Cycle 16h-1Fh Reserved Table 26. FSCM Configuration Registers Index Configuration Register or Action Type Power Well Reset 30h Activate. When bit 0 is cleared, the runtime registers of this logical device are not accessible (see Section 3.3.1 on page 40).1 R/W VDD3 00h 60h FSCM Base Address MSB register R/W VDD3 00h 61h FSCM Base Address LSB register. Bits 4-0 (for A4-0) are read only, ‘00000’. R/W VDD3 00h 70h Interrupt Number and Wake-Up on IRQ Enable register R/W VDD3 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W VDD3 03h |
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