PC87373 datasheet(7/174 Pages) NSC

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Table of Contents (Continued)

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Revision 1.1

3.2.3

Standard Configuration Register Definitions ............................................................... 36

3.2.4

Standard Configuration Registers

............................................................................ 38

3.2.5

Default Configuration Setup ........................................................................................ 39

3.3

MODULE CONTROL ................................................................................................................. 40

3.3.1

Module Enable/Disable ................................................................................................ 40

3.3.2

TRI-STATing Module Output ....................................................................................... 41

3.4

INTERNAL ADDRESS DECODING .......................................................................................... 41

3.5

PROTECTION ........................................................................................................................... 42

3.5.1

Multiplexed Pins Configuration Lock ........................................................................... 42

3.5.2

GPIO Ports Configuration Lock ................................................................................... 42

3.5.3

Fast Disable Configuration Lock .................................................................................. 42

3.5.4

Clock Control Lock ...................................................................................................... 42

3.5.5

GPIO Ports Lock .......................................................................................................... 42

3.5.6

Fan Speed Configuration Lock .................................................................................... 42

3.5.7

SWC Configuration Lock ............................................................................................. 42

3.6

3.7

PC87373 CONFIGURATION REGISTERS ............................................................................... 43

3.7.1

SuperI/O ID Register (SID) .......................................................................................... 43

3.7.2

SuperI/O Configuration 1 Register (SIOCF1) .............................................................. 44

3.7.3

SuperI/O Configuration 2 Register (SIOCF2) .............................................................. 45

3.7.4

SuperI/O Configuration 3 Register (SIOCF3) .............................................................. 46

3.7.5

SuperI/O Configuration 4 Register (SIOCF4) .............................................................. 46

3.7.6

SuperI/O Configuration 6 Register (SIOCF6) .............................................................. 47

3.7.7

SuperI/O Revision ID Register (SRID) ........................................................................ 48

3.7.8

Clock Generator Control Register (CLOCKCF) ........................................................... 48

3.8

FLOPPY DISK CONTROLLER (FDC) CONFIGURATION ........................................................ 49

3.8.1

General Description ..................................................................................................... 49

3.8.2

Logical Device 0 (FDC) Configuration ......................................................................... 49

3.8.3

FDC Configuration Register ........................................................................................ 50

3.8.4

Drive ID Register ......................................................................................................... 51

3.9

PARALLEL PORT (PP) CONFIGURATION .............................................................................. 52

3.9.1

General Description ..................................................................................................... 52

3.9.2

Logical Device 1 (PP) Configuration ............................................................................ 52

3.9.3

Parallel Port Standard Configuration Register ............................................................. 53

3.9.4

Parallel Port Modified Configuration Register .............................................................. 54

3.10

SERIAL PORT 2 CONFIGURATION ......................................................................................... 55

3.10.1

General Description ..................................................................................................... 55

3.10.2

Logical Device 2 (SP2) Configuration .......................................................................... 55

3.10.3

Serial Port 2 Configuration Register ............................................................................ 56

3.11

SERIAL PORT 1 CONFIGURATION ......................................................................................... 57

3.11.1

General Description ..................................................................................................... 57

3.11.2

Logical Device 3 (SP1) Configuration .......................................................................... 57

3.11.3

Serial Port 1 Configuration Register ............................................................................ 58

3.12

SYSTEM WAKE-UP CONTROL (SWC) CONFIGURATION ..................................................... 59

3.12.1

General Description ..................................................................................................... 59

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