PC87373 datasheet(81/174 Pages) NSC

81 / 174 page

6.0 System Wake-Up Control (SWC) (Continued)

www.national.com

Revision 1.1

6.2 FUNCTIONAL DESCRIPTION

6.2.1

External Events

General-Purpose Input/Output Events

The PC87373 device supports 12 VSB3-powered General-Purpose Input/Output events through ports GPIOE00-07 and

GPIOE10-13. VDD3- and VSB3-powered signals can be connected to the GPIO pins to become sources of external events.

AVDD3-powered signal, when used to generate an event, is internally disabled for event generation while VDD3 power is off.

It is also disabled for event generation for tEWIV after VDD3 power is restored (see Wake-Up Inputs at VDD3 Power Switching

on page 173), which prevents the detection of false events during power transitions and while the signal driver is unpowered.

For the same reasons, a VSB3-powered signal used to generate an event is enabled only tEWIV after VSB3 power is on. (When

VSB3 is off, the whole SWC module is disabled.)

Each GPIOE pin has both programmable polarity and an optional debouncer (see Figure 14). The debouncer is enabled

after the reset but can be disabled by software. The debouncing time is longer than 16 ms.

A GPIO event can generate the system interrupt (IRQ) if the event is both enabled and routed to IRQ. The status, event

enable and pending event routing bits to IRQ are implemented in the GPIO Port module (see Section 5.3 on page 75). The

status bit is set when an event of the programed type (edge or level) is detected.

A GPIO event can also generate the Power Management SCI interrupt (SIOPME). The status and event enable bits are im-

plemented in the SWC module (see Figures 14 and 15).

An active level-type event sets the status bit in registers GPE1_STS_0 for ports GPIOE07-00 and GPE1_STS_1 for ports

GPIOE13-10 (see Sections 6.4.4 and 6.4.5 on page 99). The status bit remains set even after the event becomes inactive.

The status bit is cleared only when the software writes 1 to the bit. If the event is still active when software writes 1, the status

bit remains set.

After changing the GPIOE1x pin multiplexing, clear the relevant bits in the GPE1_STS_1 register, to prevent false events

(caused by the pin multiplexing switch) from generating a wake-up event.

Figure 14. GPIO Events

Event

Enable

Event Polarity

Input

Debouncer

GPIO Event Status

Internal

Bus

Write 1 to Clear

Status

GPIO Pin Conﬁguration Register 1

Event

Debounce

Enable

Bit 6

Bit 5

(GPCFG1)

Reset

Set

GPIO Ports Module

Read

GPIO

IRQ

Routing

Control

Status

GPIO

GPIO Ports Module

SWC

PC87373 数据表(PDF) 81 Page - National Semiconductor (TI)

PC87373 数据表(HTML) 81 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载