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PC87373 数据表(PDF) 68 Page - National Semiconductor (TI) |
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PC87373 数据表(HTML) 68 Page - National Semiconductor (TI) |
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68 / 174 page  3.0 Device Architecture and Configuration (Continued) 68 www.national.com Revision 1.1 3.15.3 Fan Speed Control and Monitor Configuration Register 1 (FSCMCF1) This register is reset to 00h. Power Well: VDD3 Location: Index F0h Type: Varies per bit 74h Report no DMA assignment RO VDD3 04h 75h Report no DMA assignment RO VDD3 04h F0h Fan Speed Control and Monitor Configuration register 1 (FSCMCF1) R/W VDD3 00h F1h Fan Speed Control and Monitor Configuration register 2 (FSCMCF2) R/W VDD3 00h 1. The logical device runtime registers are maintained and all detection mechanisms are functional. Bit 76543210 Name LOCKFCF FANCTL _INV2 FANCTL _EN2 FANMON _EN2 FANCTL _INV1 FANCTL _EN1 FANMON _EN1 TRI-STATE Control Reset 00000000 Bit Type Description 7 R/W1S LOCKFCF (Lock Fan Speed Configuration). When set to 1, this bit locks the bits of the FSCMCF1 and FSCMCF2 registers by disabling writing to them (including the LOCKFCF bit itself). Once set, this bit can be cleared by VDD3 Power-Up reset (or Hardware reset). 0: R/W bits are enabled for write (default) 1: All bits are RO 6 R/W or RO FANCTL_INV2 (Fan Control Output Invert 2). When this bit is set to 1, the signal at the FANPWM2 control output is inverted (pin GPIOE4/FANPWM2). 0: Normal signal at FANPWM2 (default) 1: Inverted signal at FANPWM2 5 R/W or RO FANCTL_EN2 (Fan Control Enable 2). When this bit is set to 1, the Fan Speed Controller 2 is enabled and a PWM signal is generated at the FANPWM2 control output (pin GPIOE4/FANPWM2). 0: Disabled (default) 1: Enabled 4 R/W or RO FANMON_EN2 (Fan Monitor Enable 2). When this bit is set to 1, the Fan Speed Monitor 2 is enabled and the rate of pulses received at the FANTACH2 tachometer input is measured. 0: Disabled (default) 1: Enabled 3 R/W or RO FANCTL_INV1 (Fan Control Output Invert 1). When this bit is set to 1, the signal at the FANPWM1 control output is inverted (pin GPIOE3/FANPWM1). 0: Normal signal at FANPWM1 (default) 1: Inverted signal at FANPWM1 2 R/W or RO FANCTL_EN1 (Fan Control Enable 1). When this bit is set to 1, the Fan Speed Controller 1 is enabled and a PWM signal is generated at the FANPWM1 control output (pin GPIOE3/FANPWM1). 0: Disabled (default) 1: Enabled Table 26. FSCM Configuration Registers (Continued) Index Configuration Register or Action Type Power Well Reset |
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