PC87373 datasheet(30/174 Pages) NSC

30 / 174 page

2.0 Power, Reset and Clocks (Continued)

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Revision 1.1

Unless otherwise noted, reset references throughout the modules of the PC87373 devices default to the following resets:

For VBAT-retained functions (some SWC): VBAT Power-Up reset (within the limitations described in Section 2.2.1).

For VSB3-powered functions (GPIO ports, SWC, Glue Functions and some Conﬁguration Control): VSB Power-Up re-

set (within the limitations described in Section 2.2.2).

For VDD3-powered functions (Legacy modules, LPC, on-chip Clock Generator, FSCM and some Conﬁguration Con-

trol): VDD Power-Up reset, Hardware Reset or Software Reset (within the limitations described in Sections 2.2.3,

2.2.4 and 2.2.5).

The following sections detail the sources and effects of the various PC87373 resets.

2.2.1

VBAT Power-Up Reset

VBAT Power-Up reset is generated by an internal circuit when VBAT power is applied. An active VBAT Power-Up reset signal

is generated following a rise in the VBAT until the level of the VBAT power higher than VBATLOW is detected (see Section 13.1.5

on page 152). A VBAT Power-Up reset is generated independently of the state of the other PC87373 power supplies (VSB3,

VDD3). When VBAT Power-Up reset is active, it resets the registers whose values are retained by VBAT (some of the SWC).

2.2.2

VSB Power-Up Reset

VSB Power-Up reset is generated by an internal circuit when VSB3 power is applied. The VSB Power-Up reset time (tIRST)

lasts either 17 cycles of the 32 KHz clock domain or until the PCI_RESET signal is de-asserted, whichever occurs first. Ex-

ternal devices must wait at least tIRST before accessing the PC87373 device.

Note that the 32 KHz clock domain starts toggling t32KW +t32KVAL after VSB3 power-up. This delay must be added to the 17

clock cycles (see Low-Frequency Clock Timing on page 162).

VSB Power-Up reset performs the actions listed below and all the actions performed by VDD Power-Up reset (see Section

2.2.3). Note that VDD3 must be active during VSB3 power-up for all VDD Power-Up reset actions to be performed:

• Samples the levels of the V

BAT power pin

• Activates the relevant circuits in SWC according to the level of the V

BAT power pin

• Resets all lock bits in configuration registers and SWC

• Loads default values to VDDLOAD bits in the GPIO configuration registers

• Loads default values to the V

SB3-powered bits in the configuration registers, SWC and GPIO

• Sets up the pull-up option and the default source for the V

SB3-powered multiplexed output pins

2.2.3

VDD Power-Up Reset

VDD Power-Up reset is generated by an internal circuit when VDD3 power is turned on. VDD Power-Up reset time (tIRST) lasts

until the PCI_RESET signal is de-asserted. The Hardware reset (PCI_RESET) must be asserted for a minimum of 10 ms to

ensure that the PC87373 device operates correctly.

External devices must wait at least tIRST before accessing the PC87373. If the host processor accesses the PC87373 during

this time, the PC87373 LPC interface ignores the transaction (that is, it does not return a SYNC handshake).

VDD Power-Up reset performs the following actions:

• Puts pins with strap options into TRI-STATE and enables their internal pull-up resistors

• Samples the logic levels of the strap pins

• Executes all the actions performed by the Hardware reset (see Section 2.2.4)

2.2.4

Hardware Reset

Hardware reset is activated by the assertion (low) of the PCI_RESET input while VDD3 is “good”. When VDD3 power is off,

the PC87373 device ignores the level of the PCI_RESET input. However, the PCIRST_OUT and PCIRST_OUT2 outputs

reflect the PCI_RESET input and thus are active (low). In addition, the Hardware reset (PCI_RESET) must be asserted after

VSB power-up, as described in Section 2.2.2.

Hardware reset performs the following actions:

• Resets all lock bits in configuration registers and SWC

• Sets up the pull-up option and the default source for the V

DD3-powered multiplexed output pins

• Executes all the actions performed by the Software reset (see Section 2.2.5)

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