PC87373 datasheet(84/174 Pages) NSC

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6.0 System Wake-Up Control (SWC) (Continued)

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6.2.2

Internal Events

Keyboard and Mouse IRQ Events

Keyboard and Mouse IRQ events are detected when either the Keyboard IRQ or Mouse IRQ is asserted.

To enable the IRQ of a logical device to generate an IRQ event, the associated Enable bit (bit 4 of the configuration register

at index 70h; see Section 3.2.3 on page 36) must be set to 1. Since the Keyboard Controller (KBC) functional block is pow-

ered by VDD3, a Keyboard or Mouse IRQ event can occur only when VDD3 is present.

An active (level-type) Keyboard IRQ event sets KBD_IRQ_STS status bit; an active Mouse IRQ event sets MS_IRQ_STS

status bit. Both status bits are in GPE1_STS_3 register (see Section 6.4.7 on page 101). A status bit is cleared only when

the software writes 1 to it. If the IRQ event is active when software writes 1 to the status bit, the status bit remains set.

The ROM code used for the Keyboard Controller generates active high Keyboard and Mouse interrupts, which are used by

the SWC module.

Module IRQ Event

A Module IRQ event is detected when one of the Legacy modules (FDC, Parallel Port, Serial Ports 1 and 2, and MIDI Port)

or the Fan Speed Control and Monitor, asserts its IRQ.

To enable the IRQ of a logical device to generate an IRQ event, the associated Enable bit (bit 4 of the configuration register

at index 70h; see Section 3.2.3 on page 36) must be set to 1. Since the Legacy modules and the Fan Speed Monitor are

MOD_IRQ_STS status bit in GPE1_STS_3 register is set by an IRQ that is asserted by one of the Legacy modules or the

Fan Speed Monitor (see Section 6.4.7 on page 101). The status bit is cleared only when the software writes 1 to it. If the

Module IRQ event is active when software writes 1 to the status bit, the status bit remains set.

6.2.3

Sleep States

The PC87373 identifies the current system sleep state, by decoding the levels of the SLP_S3 and SLP_S5 pins. The levels

of these pins are generated by the system ACPI controller located in an external device. Table 31 shows the decoding of

the logic levels of the SLP_S3 and SLP_S5 pins.

6.2.4

SCI and IRQ Interrupts

The SCI (SIOPME) pin is the Power Management interrupt defined by ACPI.

All external and internal events are exclusively processed by the SWC to generate the Power Management interrupt, SCI.

Each active event sets a status bit in GPE1_STS_0 to GPE1_STS_3 registers (see Sections 6.4.4 to 6.4.7 on page 99).

For each status bit, the SWC holds an enable bit in GPE1_EN_0 to GPE1_EN_3 registers. A set status bit can set PME_STS

bit in GPE1_STS register (see Section 6.4.2 on page 98) only when its related enable bit is set. A set PME_STS bit can

cause the assertion of the SCI interrupt only when PME_EN bit in GPE1_EN register is set (see Section 6.4.3 on page 98).

The SCI interrupt is independent of the system sleep state.

The SIOPME signal can be inverted to generate an active high SCI interrupt. In addition, the output buffer of the SIOPME

pin can be configured as either push-pull or open-drain, to allow sharing with external SCI interrupt sources.

Figure 15 shows SCI generation.

Table 31. SLP_S3, SLP_S5 Decoding

SLP_S3

SLP_S5

System Sleep State

S0, S1 or S2

Illegal combination

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