PC87373 datasheet(86/174 Pages) NSC

86 / 174 page

6.0 System Wake-Up Control (SWC) (Continued)

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Standard LED Control

The Standard LED control is the default LED control option when VBAT pin is connected to ground (VSS). Two regular LEDs

must be connected to the GRN_LED and the YLW_LED pins, according to configuration “b” (Active High) in Figure 16.

In this option, LED operation is controlled by the bits of SLEDCTL register (at offset 00h; see Section 6.3.2 on page 89) and

by the SLP_S5 pin. When the system is in sleep state S5 (SLP_S5 = 0), both LEDs are off. GRN_YLW bit selects the active

LED (on or blinking) of the two; the other LED is off. BLINK bit selects the operation mode of the active LED as either con-

stantly on or blinking at 0.667 Hz with a duty cycle of 41.7% (on time percent of the blink cycle).

Table 34 on page 89 shows the states of the GRN_LED and YLW_LED pins. The LEDs are connected according to config-

uration “b” (see Figure 16); therefore, a LED is on when the pin is TRI-STATEd and off when the pin is at low level (0).

Advanced LED Control

In the Advanced LED control option, one dual-color LED or two regular LEDs can be connected to the GRN_LED and the

YLW_LED pins, using any of the configurations shown in Figure 16. LEDCFG and LEDPOL bits in ALEDCTL register (at

offset 02h; see Section 6.3.4 on page 91) must be set to reflect the connection configuration of the LEDs.

LEDCFG bit selects either configurations “a” and “b” (two regular LEDs are connected between each pin and ground or

VSUPP) or configuration “c” (one dual-color LED is connected between the GRN_LED and YLW_LED pins). LEDPOL bit se-

lects the polarity of the On state at both pins (GRN_LED and YLW_LED). Table 32, shows the value of LEDCFG and LED-

POL bits for each LED connection configuration in Figure 16, and also the state of the GRN_LED and YLW_LED pins for

which the LED(s) are On.

The LEDMOD field controls the operation mode of GRN_LED and YLW_LED pins in each system power state (see Table 35

on page 91). The system power state is identiﬁed either by the status of the VDD3 power supply or by the current system

sleep state:

• ‘00’ – The behavior of the GRN_LED and YLW_LED pins is controlled solely by software by the setting of the

GRNBLNK and YLWBLNK fields.

• ‘01’ – The behavior of the GRN_LED and YLW_LED pins is controlled by the status of the V

DD3 supply and by software.

In the Power Off state (VDD3 off), the GRN_LED behaves according to the setting of the GRNBLNK field, but the

YLW_LED blinks at a 1 Hz rate with a 50% duty cycle;

In the Power On state (VDD3 on), each LED behaves according to the setting of its xxxBLNK field.

• ‘10’ – The behavior of the GRN_LED and YLW_LED pins is controlled by the S5 sleep state and by software.

In S5 sleep state, both LEDs are off;

In S3 - S0 sleep states, each LED behaves according to the setting of its xxxBLNK field.

• ‘11’ – The behavior of the GRN_LED and YLW_LED pins is controlled by the status of the V

DD3 supply and by software.

In the Power Off state (VDD3 off), both LEDs are off;

In Power On state (VDD3 on), each LED behaves according to the setting of its xxxBLNK field.

The status of the VDD3 power supply is detected by internal circuits, which identify the Power Off and Power On states (see

Section 2.1.2 on page 27).

The current system sleep state is decoded from the levels of the SLP_S3 and SLP_S5 pins (see Section 6.2.3 on page 84).

Only sleep state S5 is relevant.

The GRNBLNK and YLWBLNK fields in LEDBLNK register (at offset 03h; see Section 6.3.6 on page 93) control the On/Off

state or the blinking rate of the GRN_LED and YLW_LED pins, respectively. For each LED pin, a different blink rate can be

selected. Different blink rates can also be selected for the dual-color LED mode (LEDCFG = 0).

Table 32. LEDs “On” Polarity as a Function of LEDCFG and LEDPOL

LEDCFG

LEDPOL

GRN_LED

YLW_LED

Connection (See Figure 16)

TRI-STATE

“c”, Green anode to GRN_LED pin

TRI-STATE

“c”, Yellow anode to GRN_LED pin

TRI-STATE

“b”

1100

“a”

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