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PC87373 数据表(PDF) 29 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 PC87373
功能描述  LPC SuperI/O with Glue Functions
PDF  174 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

PC87373 数据表(HTML) 29 Page - National Semiconductor (TI)

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2.0 Power, Reset and Clocks (Continued)
29
www.national.com
Revision 1.1
The decoupling capacitor of the Standby 5V supply (V
SB5) pin
The decoupling capacitor of the on-chip Core power converter (V
CORF) pin
The decoupling capacitor of the Backup battery (V
BAT) pin
Note that a low-impedance ground layer also improves noise isolation.
Decoupling Capacitors. The following decoupling capacitors must be used in order to reduce EMI and ground bounce:
Main power supply (V
DD3): Place one capacitor of 0.1 µF on each VDD3-VSS pin pair as close to the pin as possible. In
addition, place one 10
−47 µF tantalum capacitor on the common net as close to the chip as possible.
Standby power supply (V
SB3): Place one capacitor of 0.1 µF on each VSB3-VSS pin pair as close to the pin as possible.
In addition, place one 10
−47 µF tantalum capacitor on the common net as close to the chip as possible.
Standby 5V supply (V
SB5): Place one capacitor of 0.1 µF on the VSB5-VSS pin pair as close to the pin as possible.
On-chip Core power converter (V
CORF): Place one 1 µF ceramic capacitor on the VCORF-VSS pin pair as close to the pin
as possible.
Backup battery (V
BAT): Place one capacitor of 0.1 µF on the VBAT pin as close to the pin as possible.
Figure 2. Decoupling Capacitors Connection
2.2 RESET SOURCES AND TYPES
The PC87373 device has five reset sources:
V
BAT Power-Up Reset - activated when VBAT is powered up.
V
SB Power-Up Reset - activated when VSB3 is powered up.
V
DD Power-Up Reset - activated when VDD3 is powered up.
Hardware Reset - activated when the PCI_RESET input is asserted (low).
Software Reset - triggered by SWRST bit in SIOCF1 register (see Section 3.7.2 on page 44); SWRST bit is set by the
host through the LPC interface.
VDD3
PC87373
0.1
µF
8
6
0.1
µF
29
31
0.1
µF
46
49
0.1
µF
58
60
VSS
VDD3
VDD3
VDD3
VSS
VSS
VSS
+
10-47
µF
Main 3.3V
VSB3
VSS
VSB3
VSB3
VSS
VSS
0.1
µF
78
76
0.1
µF
96
93
0.1
µF
110
107
+
10-47
µF
Standby 3.3V
1
µF
97
VCORF
VSB5
0.1
µF
71
Standby 5V
Backup
0.1
µF
98
VBAT
Battery



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