PC87373 datasheet(56/174 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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3.10.3 Serial Port 2 Configuration Register

This register is reset by hardware to 02h.

Power Well: VDD

Location:

Index F0h

Type:

R/W

Bit

76543210

Name

Bank

Select

Enable

Reserved

Busy

Indicator

Power

Mode

Control

TRI-STATE

Control

Reset

00000010

Bit

Description

Bank Select Enable. Enables bank switching for Serial Port 2.

0: All attempts to access the extended registers in Serial Port 2 are ignored (default)

1: Enables bank switching for Serial Port 2

6-3

Reserved.

Busy Indicator. This read only bit can be used by power management software to decide when to power-down

the Serial Port 2 logical device.

0: No transfer in progress (default)

1: Transfer in progress

Power Mode Control. The logical device can be active in two modes:

0: Low Power mode: When the logical device is active in Low Power mode,

- The Low Serial Port 2 clock is disabled.

- The output signals are set to their default states.

- The RI input signal can be programed to generate an interrupt.

- Registers are maintained (unlike the activation bit in Index 30h, which also prevents access to Serial Port 2

registers).

1: Normal Power mode: When the logical device is active in Normal Power mode,

- Serial Port 2 clock enabled.

- Serial Port 2 is functional when the logical device is active (default).

TRI-STATE Control. When this bit is set to 1 and the logical device is inactive, the logical device output pins

are in TRI-STATE (see Section 3.3.2 on page 41).

0: Normal outputs (default)

1: TRI-STATE outputs when the logical device is inactive

PC87373 数据表(PDF) 56 Page - National Semiconductor (TI)

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