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PC87373 数据表(PDF) 16 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 PC87373
功能描述  LPC SuperI/O with Glue Functions
PDF  174 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

PC87373 数据表(HTML) 16 Page - National Semiconductor (TI)

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1.0 Signal/Pin Connection and Description (Continued)
16
www.national.com
Revision 1.1
1.4 DETAILED SIGNAL/PIN DESCRIPTIONS
This section describes all signals of the PC87373 device. The signals are organized by functional group.
1.4.1
LPC Interface
Signal
Pin(s) I/O Buffer Type Power Well
Description
LAD3-0
57,59
61,62
I/O
INPCI/OPCI
VDD3
LPC Address-Data. Multiplexed command, address bi-directional
data and cycle status.
PCI_CLK
55
I
INPCI
VDD3
LPC Clock. PCI clock used for the LPC bus (up to 33 MHz).
LFRAME
56
I
INPCI
VDD3
LPC Frame. Low pulse indicates the beginning of a new LPC
cycle or termination of a broken cycle.
LDRQ
54
O
OPCI
VDD3
LPC DMA Request. Encoded DMA request for LPC interface.
PCI_RESET
63
I
INPCI
VDD3
LPC Reset. PCI system reset used for the LPC bus (Hardware
Reset).
SER_IRQ
53
I/O
INPCI/OPCI
VDD3
Serial IRQ. The interrupt requests are serialized over a single pin,
where each IRQ level is delivered during a designated time slot.
LPCPD
52
I
INPCI
VDD3
Power Down. Indicates that power to the LPC interface is about
to be turned off. When LPCPD functionality is not required, an
internal pull-up resistor allows this pin to be left floating.
PCIRST_OUT
73
O
O14/14
VSB3
PCI Reset Output. PCI system reset. PCIRST_OUT is a
buffered copy of PCI_RESET when VDD3 is on, and it is held at
low level when VDD3 is off.
PCIRST_OUT2 74
O
O14/14
VSB3
PCI Reset Output 2. PCI system reset (same behavior as
PCIRST_OUT above).
IDE_RSTDRV64
O
OD6
VDD3
IDE Reset Output. IDE drive reset. IDE_RSTDRV is a buffered
copy of PCI_RESET when VDD3 is on, and it is floating when
VDD3 is off.



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