PC87373 datasheet(42/174 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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Revision 1.1

3.5 PROTECTION

The PC87373 device provides features to protect the hardware configuration from changes made by application software

running on the host.

The protection is activated by the software setting a “sticky” lock bit. Each lock bit protects a group of configuration bits lo-

cated either in the same register or in different registers. When the lock bit is set, the lock bit and all the protected bits be-

come read only and cannot be further modified by the host through the LPC bus. All the lock bits are reset by Power-Up

reset, thus unlocking the protected configuration bits.

The bit locking protection mechanism is optional.

The protected groups of configuration bits are described below.

3.5.1

Multiplexed Pins Configuration Lock

Protects the configuration of all the multiplexed device pins.

Lock bit:

LOCKMCF in SIOCF1 register (Device Configuration).

Protected bits: IOWAIT in SIOCF1 register and all bits of the SIOCF2, SIOCF3 and SIOCF4 registers (Device Configura-

tion).

3.5.2

GPIO Ports Configuration Lock

Protects the configuration (but not the data) of all the GPIO Ports.

Lock bit:

LOCKGCF in SIOCF1 register (Device Configuration).

Protected bits for each GPIO Port: All bits of GPCFG1, GPEVR, GPCFG2 and GPMODE registers except LOCKCFP bit

(Device Configuration).

3.5.3

Fast Disable Configuration Lock

Protects the Fast Disable bits for all the Legacy modules.

Lock bit:

LOCKFDS in SIOCF6 register (Device Configuration).

Protected bits: All bits of the SIOCF6 register, except General-Purpose Scratch bits and GLOBEN bit in SIOCF1 register

(Device Configuration).

3.5.4

Clock Control Lock

Protects the Clock Generator control bits.

Lock bit:

HFCGEN in CLOCKCF register (Device Configuration).

Protected bits: All bits of the CLOCKCF register (Device Configuration).

3.5.5

GPIO Ports Lock

Protects the configuration and data of all the GPIO Ports.

Lock bit:

LOCKCFP in GPCFG1 register, for each GPIO Port (Device Configuration).

Protected bits for each GPIO Port: PUPCTL, OUTTYPE and OUTENA in GPCFG1 register; all bits of the GPCFG2 register

(Device Configuration); the corresponding bit (to the port pin) in GPDO and GPDIO registers (GPIO Ports).

3.5.6

Fan Speed Configuration Lock

Protects the Fan Speed Control and Monitor configuration bits.

Lock bit:

LOCKFCF in FSCMCF1 register (Device Configuration).

Protected bits: All bits of the FSCMCF1 and FSCMCF2 registers (Device Configuration).

3.5.7

SWC Configuration Lock

Protects the configuration of the SWC module, including the Keyboard and Mouse wake-up configuration.

Lock bit:

LOCKSCF in SWC_CTL register (System Wake-Up Control).

Protected bits: BLINK and GRN_YLW bits in the SLEDCTL register;

all bits of the SWC_CTL, ALEDCTL, LEDBLNK, XLEDCTL, KBDWKCTL, PS2CTL and

PS2KEY0

−7 registers (System Wake-Up Control).

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PC87373 数据表(PDF) 42 Page - National Semiconductor (TI)

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