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PC87373 数据表(PDF) 63 Page - National Semiconductor (TI) |
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PC87373 数据表(HTML) 63 Page - National Semiconductor (TI) |
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63 / 174 page  3.0 Device Architecture and Configuration (Continued) 63 www.national.com Revision 1.1 3.14.2 Logical Device 7 (GPIO) Configuration Table 24 lists the configuration registers that affect the GPIO. Only the last five registers (F0h-F3h and F8h) are described here. See Section 3.2.3 on page 36 for a detailed description of the other configuration registers. The standard configuration registers are powered by VDD3; however, the specific configuration registers are powered by VSB3. Figure 8 shows the organization of registers GPCFG1-2, GPEVR and GPMODE: Figure 8. Organization of GPIO Pin Registers GPCFG1-2, GPEVR and GPMODE Table 24. GPIO Configuration Register Index Configuration Register or Action Type Power Well Reset 30h Activate (see Section 3.2.3 on page 36) R/W VDD3 00h 60h Base Address MSB register R/W VDD3 00h 61h Base Address LSB register. Bits 4-0 (for A4-0) are read-only, ‘00000’. R/W VDD3 00h 70h Interrupt Number and Wake-Up on IRQ Enable register R/W VDD3 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W VDD3 03h 74h Report no DMA assignment RO VDD3 04h 75h Report no DMA assignment RO VDD3 04h F0h GPIO Pin Select register (GPSEL) R/W VSB3 00h F1h GPIO Pin Configuration register 1 (GPCFG1) Varies per bit VSB3 00h F2h GPIO Pin Event Routing register (GPEVR) R/W or RO VSB3 00h F3h GPIO Pin Configuration register 2 (GPCFG2) R/W or RO VSB3 00h F8h GPIO Mode Select register (GPMODE) R/W or RO VSB3 01h GPIO Pin Configuration Registers Pin Select Port Select Port 0, Pin 0 GPIO Pin Select Register GPIO Pin Event Routing Register Port 0, Pin 7 Port 0 Port 1 Pin 0 Pin 7 Port 1, Pin 0 Pin 0 Pin 7 Port 0, Pin 0 Port 1, Pin 0 Port 0, Pin 7 (Index F0h) (Index F1h) (Index F2h) (Index F3h) Port 0 Port 1 |
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