PC87373 datasheet(6/174 Pages) NSC

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Revision 1.1

Table of Contents

1.0

Signal/Pin Connection and Description

1.1

CONNECTION DIAGRAMS

................................................................................................ 13

1.2

BUFFER TYPES AND SIGNAL/PIN DIRECTORY .................................................................... 14

1.3

PIN MULTIPLEXING ................................................................................................................. 15

1.4

DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................ 16

1.4.1

LPC Interface ..............................................................................................................16

1.4.2

Serial Port 1 and Serial Port 2 (UART1 and UART2)

............................................. 17

1.4.3

Parallel Port

..............................................................................................................18

1.4.4

Floppy Disk Controller (FDC)

.................................................................................... 19

1.4.5

Keyboard and Mouse Controller (KBC)

..................................................................... 20

1.4.6

Game Port (GMP) ...................................................................................................... 20

1.4.7

Musical Instrument Digital Interface (MIDI) Port ........................................................ 20

1.4.8

General-Purpose I/O (GPIO) ...................................................................................... 21

1.4.9

Fan Speed Control and Monitor (FSCM) ................................................................... 21

1.4.10

System Wake-Up Control (SWC)

.............................................................................. 22

1.4.11

Clocks

..................................................................................................................... 22

1.4.12

Glue Functions ........................................................................................................... 23

1.4.13

Configuration Straps and Testing ............................................................................... 24

1.4.14

Power and Ground

.................................................................................................... 25

1.5

INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................ 25

2.0

Power, Reset and Clocks

2.1

POWER ..................................................................................................................................... 27

2.1.1

Power Planes .............................................................................................................. 27

2.1.2

Power States ...............................................................................................................27

2.1.3

Power Connection and Layout Guidelines .................................................................. 28

2.2

RESET SOURCES AND TYPES ............................................................................................... 29

2.2.1

VBAT Power-Up Reset ................................................................................................. 30

2.2.2

VSB Power-Up Reset .................................................................................................. 30

2.2.3

VDD Power-Up Reset .................................................................................................. 30

2.2.4

Hardware Reset ........................................................................................................... 30

2.2.5

Software Reset ............................................................................................................ 31

2.3

CLOCK DOMAINS ..................................................................................................................... 31

2.3.1

LPC Domain ................................................................................................................ 31

2.3.2

48 MHz Domain ........................................................................................................... 31

2.3.3

32 KHz Domain ........................................................................................................... 32

2.4

TESTABILITY SUPPORT ..........................................................................................................32

2.4.1

ICT ............................................................................................................................... 32

2.4.2

XOR Tree Testing ........................................................................................................ 33

3.0

Device Architecture and Configuration

3.1

OVERVIEW ............................................................................................................................... 34

3.2

CONFIGURATION STRUCTURE AND ACCESS ..................................................................... 34

3.2.1

The Index-Data Register Pair ...................................................................................... 34

3.2.2

Banked Logical Device Registers Structure ................................................................ 35

PC87373 数据表(PDF) 6 Page - National Semiconductor (TI)

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