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PC87373 数据表(PDF) 32 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 PC87373
功能描述  LPC SuperI/O with Glue Functions
PDF  174 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

PC87373 数据表(HTML) 32 Page - National Semiconductor (TI)

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2.0 Power, Reset and Clocks (Continued)
32
www.national.com
Revision 1.1
Figure 3. 32 KHz and 48 MHz Clock Domains (Simplified Diagram)
2.3.3
32 KHz Domain
The 32 KHz clock domain, and the modules using it, are supplied by the Standby and Core power planes. Therefore, this
clock domain is active whenever the VSB3 and VCORF power supplies are on.
The 32 KHz clock domain is sourced by the CLOCKI32 pin. The clock signal from the CLOCKI32 pin passes through a Clock
Filter. The 32 KHz clock domain signal is held low by the 32KVAL output of the Clock Filter until a valid 32.768 KHz clock is
available at the CLOCKI32 pin. The 32 KHz clock domain signal starts toggling t32KW +t32KVAL after VSB3 Power-Up (Low-
Frequency Clock Timing on page 162).
2.4 TESTABILITY SUPPORT
The PC87373 device supports two testing techniques:
In-Circuit Testing (ICT)
XOR Tree Testing
2.4.1
ICT
The In-Circuit Testing (ICT) technique, also known as “bed-of-nails”, injects logic patterns to the input pins of the devices
mounted on the tested board. It then checks their outputs for the correct logic levels.
The PC87373 supports this testing technique by floating (TRI-STATing) all the device pins. This prevents “back-driving” the
PC87373 pins by the ICT tester when a device normally controlled by PC87373 is tested (device inputs are driven by the
ICT tester).
To enter TRI-STATE mode, the TRIS pin must be pulled low (by a 10 K
Ω resistor to V
SS), and the TEST pin must be left
unconnected after both VDD3 and VSB3 power supplies are turned on. In addition, the PCI_RESET pin must be held low for
at least 10 ms (see VSB Power-Up Reset on page 159 and VDD Power-Up Reset on page 160). After PCI_RESET is de-
asserted, all the device output and I/O pins are floated (TRI-STATEd); exceptions to this are the power supply pins (VDD3,
VSB3, VSS, VCORF, VBAT), analog pins (VSB5, REF5V, REF5V_STBY), RSMRST, which do not float in TRI-STATE mode.
Clock
Generator
14.31818 MHz
CLOCKI14
Functions
Internal
48 MHz
CKVALID
EN
(VDD3)
CLOCKI32
Functions
Internal
Filter
Clock
32.768 KHz
32.768 KHz
32KVAL
32 KHz Domain
48 MHz Domain
HFCGEN



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