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V-ACPI I/O REGISTER SPACE

The register space designated as V-ACPI I/O does not

physically exist in the CS5530. ACPI is supported in the

CS5530 by virtualizing this register space, called V-ACPI.

In order for ACPI to be supported, the V-ACPI VSA mod-

ule must be included in the BIOS. The register descrip-

tions that follow, are supplied here for reference only.

FixedFeature Spaceregisters are requiredtobeimple-

mented by all ACPI-compatible hardware. The Fixed Fea-

ture registers in the VSA/ACPI solution are mapped to

normal I/O space starting at offset AC00h; however, the

designer can relocate this register space at compile time,

hence are hereafter referred to as ACPI_BASE. Registers

within V-ACPI (Virtualized ACPI) I/O space must only be

accessed on their defined boundaries. For example, byte

aligned registers must not be accessed via WORD I/O

instructions, WORD aligned registers must not be

accessed as DWORD I/O instructions, etc.

The V-ACPI I/O Register Space can be broken up into

major blocks:

• PM Event Block 1A (PM1A_EVT_BLK)

• PM Event Block 1A Control (PM1A_CNT_BLK)

• Processor Register Block (P_BLK)

• Command Block (CMD_BLK)

• Test/Setup Block (TST/SETUP_BLK)

• General Purpose Enable 0 Block (GPE0_BLK)

PM1A_EVT_BLK is 32-bit aligned and contains two 16-bit

registers, PM1A_STS and PM1A _EN.

PM1A_CNT_BLK is 32-bit aligned and contains one 16-

bit register, PM1A_CNT. PM1A_CNT contains the Fixed

Feature control bits used for various power management

enables and as communication flags between BIOS and

the ACPI OS.

P_BLK is 32-bit aligned (one register block per processor)

and contains two registers P_CNT and P_LVL2. P_LVL3

is currently not supported.

- P_CNT (Processor Control) - 16-bit register,

Controls process duty cycle via CPU clock throttling.

DUTY_WIDTH = 3 (can be widened)

DUTY_OFFSET = 0

- P_LVL2 (Enter C2 Power State) - 8-bit, read only

C2 power state.

CMD_BLK contains one 8-bit register SMI_CMD which

interprets and processes the ACPI commands (defined in

Fixed ACPI Description Table, refer to ACPI Specification,

Section 5.2.5).

TST/SETUP_BLK is provided by the VSA technology

code and contains two registers, SETUP_IDX and

SETUP_DATA for the purpose of configuring the CS5530.

Specifically, this pair of registers enables system software

to mapGPIO pinsonthe CS5530toPM1A_STSand

GPE0_STS register bits.

GPE0_BLK has registers used to enable system software

to configure GPIO (General Purpose I/O) pins to generate

SCI interrupts. GPE0_BLK is a 32-bit block aligned on a

4-byte

boundary.

contains

two

16-bit

registers,

GPE0_STS and GPE0_EN, each of which must be con-

figured by the BIOS POST. In order for a GPE0_STS bit to

generate an SCI, the corresponding enable bit in

GPE0_EN must be set.

Table 4-32 give the bit formats of the V-ACPI I/O registers.

Table 4-32. V-ACPI Registers

Bit

Description

ACPI_BASE 00h-03h

P_CNT — Processor Control Register (R/W)

Reset Value = 00000000h

31:5

Reserved: Always 0.

THT_EN: Enables throttling of the clock based on the CLK_VAL field.

Reserved: Always 0.

2:0

CLK_VAL: Clock throttling value: CPU duty cycle =

000 = Reserved

100 = 50%

001 = 12.5%

101 = 62.5%

010 = 25%

110 = 75%

011 = 37.5%

111 = 87.5%

ACPI_BASE 04h

P_LVL2 — Enter C2 Power State Register (RO)

Reset Value = 00h

Reading this 8-bit read only register causes the processor to enter the C2 power state. Reads of P_LVL2 return 0. Writes have no

effect.

ACPI_BASE 05h

Reserved

Reset Value = 00h

ACPI_BASE 06h

SMI_CMD — OS/BIOS Requests Register (R/W)

Reset Value = 00h

Interpret and process the ACPI commands (defined in Fixed ACPI Description Table, refer to ACPI Specification, Section 5.2.5):

0x01 - ACPI_ENABLE

0x02 - ACPI_DISABLE

0x03 - S4BIOS_REQ (optional)

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