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218

Revision 4.1

ACPI_BASE 07h

Reserved

Reset Value = 00h

ACPI_BASE 08h-09h

PM1A_STS — PM1A Status Register (R/W)

Reset Value = 0000h

WAKE_STS: Wake Status: Set when system was in sleep state and an enabled wakeup occurs.

14:11

Reserved

RTC_STS: Real Time Clock Status: This bit changes to 1 if an RTC alarm causes a wake up event. This bit is only set

upon wakeup from a sleep state and IRQ8 is asserted by the RTC. Refer to Table 4-35.

SLPBTN_STS: Sleep Button Status (Optional): This bit changes to 1 when the sleep button is pressed. If SLPBTN_EN is

set, an SCI interrupt is generated.

This bit must be configured to be set by a GPIO pin using SETUP_IDX values 0x10-0x17 in order to be set. Refer to Table

4-34.

PWRBTN_STS: Power Button Status: This bit is set when power button is pressed. If PWRBTN_EN is set, an SCI inter-

rupt is asserted.

This bit must be configured to be set by a GPIO pin using SETUP_IDX values 0x10-0x17 in order to be set. Refer to Table

4-34.

7:6

Reserved

GBL_STS: Global Status: The BIOS sets GBL_STS to 1 to release its global lock and return control to the ACPI OS. At

the same time GBL_STS is set, the BIOS generates an SCI.

BM_STS: Bus Master Status: This bit is not supported by V-ACPI.

3:1

Reserved

TMR_STS: ACPI Timer Status: This bit changes to 1 whenever bit 23 of the ACPI timer (F1BAR+Memory Offset 1Ch or

I/O Port 121Ch in Silicon Rev 1.3 and above) changes state. The ACPI OS is responsible for clearing TMR_STS.

If TMR_EN is also set then a SCI interrupt is asserted.

Note: Status bits are “sticky”. A write of a one (1) to a given bit location will reset the bit.

ACPI_BASE 0Ah-0Bh

PM1A_EN — PM1A Enable Register (R/W)

Reset Value = 0000h

15:11

Reserved

RTC_EN: Real Time Clock Enable: If set, an SCI is asserted when RTC_STS changes to 1.

SLPBTN_EN: Sleep Button Enable (Optional): If set, an SCI is asserted when SLPBTN_STS changes to 1.

PWRBTN_EN: Power Button Enable: If set, an SCI is asserted when PWRBTN_STS changes to 1.

7:6

Reserved

GBL_EN: Global Lock Enable: If set, writing a 1 to GBL_STS causes an SCI to be asserted.

4:1

Reserved

TMR_EN: ACPI Timer Enable: If set, an SCI is asserted when bit 23 of the ACPI timer (F1BAR+Memory Offset 1Ch or

I/O Port 121Ch in Silicon Rev 1.3 and above) changes state.

ACPI_BASE 0Ch-0Dh

PM1A_CNT — PM1A Control Register (R/W)

Reset Value = 0000h

15:14

Reserved

SLP_EN (WO): Sleep Enable (Write Only): Setting this bit causes the system to enter the sleep state defined by

SLP_TYPx. Reads of this bit always return zero.

12:10

SLP_TYPx: Sleep Type: Defines the type of sleep state the system enters when SLP_EN is set.

000 = Sleep State S0 (Full on)

100 = Sleep State S4

001 = Sleep State S1

101 = Sleep State S5 (Soft off)

010 = Sleep State S2

110 = Reserved

011 = Reserved

111 = Reserved

9:3

Reserved

GBL_RLS (WO): Global Lock Release (Write Only): Used by ACPI OS to raise an event to the BIOS software (SMI).

Used by ACPI driver to indicate a release of the global lock and the setting of the pending bit in the FACS table (refer to

ACPI Specification, Section 5.2.8).

BM_RLD: This bit is not supported by V-ACPI.

SCI_EN: System Controller Interrupt Enable: Selects whether power management events are SCI or SMI. Set by hard-

ware based on an ACPI_ENABLE/ACPI_DISABLE written to the SMI_CMD port.

Table 4-32. V-ACPI Registers (Continued)

Bit

Description

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