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CS5530 数据表(PDF) 216 Page - National Semiconductor (TI) |
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CS5530 数据表(HTML) 216 Page - National Semiconductor (TI) |
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216 / 241 page  www.national.com 216 Revision 4.1 Register Descriptions (Continued) Table 4-31. Miscellaneous Registers Bit Description I/O Ports 170h-177h/376h-377h Secondary IDE Registers (R/W) When the local IDE functions are enabled, reads or writes to these registers cause the local IDE interface signals to operate according to their configuration rather than generating standard ISA bus cycles. I/O Ports 1F0h-1F7h/3F6h-3F7h Primary IDE Registers (R/W) When the local IDE functions are enabled, reads or writes to these registers cause the local IDE interface signals to operate according to their configuration rather than generating standard ISA bus cycles. I/O Port 4D0h Interrupt Edge/Level Select Register 1 (R/W) Reset Value = 00h 7 IRQ7 Edge or Level Select: Selects PIC IRQ7 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 6 IRQ6 Edge or Level Select: Selects PIC IRQ6 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 5 IRQ5 Edge or Level Select: Selects PIC IRQ5 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 4 IRQ4 Edge or Level Select: Selects PIC IRQ4 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 3 IRQ3 Edge or Level Select: Selects PIC IRQ3 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 2 Reserved: Set to 0. 1 IRQ1 Edge or Level Select: Selects PIC IRQ1 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 0 Reserved: Set to 0. Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides this setting. 2. This bit is provided to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared). I/O Port 4D1h Interrupt Edge/Level Select Register 2 (R/W) Reset Value = 00h 7 IRQ15 Edge or Level Select: Selects PIC IRQ15 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 6 IRQ14 Edge or Level Select: Selects PIC IRQ14 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 5 Reserved: Set to 0. 4 IRQ12 Edge or Level Select: Selects PIC IRQ12 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 3 IRQ11 Edge or Level Select: Selects PIC IRQ11 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 2 IRQ10 Edge or Level Select: Selects PIC IRQ10 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 1 IRQ9 Edge or Level Select: Selects PIC IRQ9 sensitivity configuration: 0 = Edge; 1 = Level. (Notes 1 and 2) 0 Reserved: Set to 0. Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides this setting. 2. This bit is provided to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared). I/O Port 121Ch-121Fh (Note) ACPI Timer Count Register (RO) Reset Value = 00FFFFFCh ACPI_COUNT (Read Only): This read-only register provides the ACPI counter. The counter counts at 14.31818/4 MHz (3.579545 MHz). If SMI generation is enabled via F0 Index 83h[5], an SMI is generated when the MSB toggles. The MSB toggles every 2.343 seconds. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported is at F0 Index 87h/F7h[0]. 31:24 Reserved: Always returns 0. 23:0 Counter Note: The ACPI Timer Count Register is accessible through I/O Port 121Ch in Silicon Revision 1.3 and above. Otherwise read at F1BAR+Offset 1Ch. |
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