LAN9252SLASHML datasheet(175/329 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001909A-page 175

LAN9252

MDIO Manageable Device (MMD) Registers

The device MMD registers adhere to the IEEE 802.3-2008 45.2 MDIO Interface Registers specification. The MMD reg-

isters are not memory mapped. These registers are accessed indirectly via the PHY x MMD Access Control Register

(PHY_MMD_ACCESS) and PHY x MMD Access Address/Data Register (PHY_MMD_ADDR_DATA). The supported

MMD device addresses are 3 (PCS), 7 (Auto-Negotiation), and 30 (Vendor Specific). Table 11-14, "MMD Registers"

details the supported registers within each MMD device.

TABLE 11-14: MMD REGISTERS

MMD DEVICE

ADDRESS

(IN DECIMAL)

INDEX

(IN DECIMAL)

(PCS)

PHY x PCS MMD Devices Present 1 Register (PHY_PCS_MMD_PRE-

SENT1_x)

PHY x PCS MMD Devices Present 2 Register (PHY_PCS_MMD_PRE-

SENT2_x)

32784

PHY x Wakeup Control and Status Register (PHY_WUCSR_x)

32785

PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x)

32786

PHY x Wakeup Filter Configuration Register B (PHY_WUF_CFGB_x)

32801

PHY x Wakeup Filter Byte Mask Registers (PHY_WUF_MASK_x)

32802

32803

32804

32805

32806

32807

32808

32865

PHY x MAC Receive Address A Register (PHY_RX_ADDRA_x)

32866

PHY x MAC Receive Address B Register (PHY_RX_ADDRB_x)

32867

PHY x MAC Receive Address C Register (PHY_RX_ADDRC_x)

(Auto-Negotiation)

PHY x Auto-Negotiation MMD Devices Present 1 Register

(PHY_AN_MMD_PRESENT1_x)

PHY x Auto-Negotiation MMD Devices Present 2 Register

(PHY_AN_MMD_PRESENT2_x)

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