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LAN9252/ML 数据表(PDF) 25 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 25 Page - Microchip Technology |
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25 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 25 LAN9252 1Latch In LATCH_IN VIS This pin is the external data latch signal. The input data is sampled each time a rising edge of LATCH_IN is recognized. 1 Watchdog Trigger WD_TRIG VO8 This pin is the SyncManager Watchdog Trigger out- put. Note: The signal is not driven (high imped- ance) until the EEPROM is loaded. 1 Watchdog State WD_STATE VO8 This pin is the SyncManager Watchdog State out- put. A 0 indicates the watchdog has expired. Note: The signal is not driven (high imped- ance) until the EEPROM is loaded. 1 Start of Frame SOF VO8 This pin is the Start of Frame output and indicates the start of an Ethernet/EtherCAT frame. Note: The signal is not driven (high imped- ance) until the EEPROM is loaded. 1 End of Frame EOF VO8 This pin is the End of Frame output and indicates the end of an Ethernet/EtherCAT frame. Note: The signal is not driven (high imped- ance) until the EEPROM is loaded. 1 Output Enable OE_EXT VIS This pin is the Output Enable input. When low, it clears the output data. TABLE 3-11: EEPROM PIN DESCRIPTIONS Num Pins Name Symbol Buffer Type Description 1 EEPROM I2C Serial Data Input/Output EESDA VIS/VOD8 When the device is accessing an external EEPROM this pin is the I2C serial data input/open-drain out- put. Note: This pin must be pulled-up by an exter- nal resistor at all times. 1 EEPROM I2C Serial Clock EESCL VOD8 When the device is accessing an external EEPROM this pin is the I2C clock open-drain output. Note: This pin must be pulled-up by an exter- nal resistor at all times. TABLE 3-10: ETHERCAT DIGITAL I/O AND GPIO PIN DESCRIPTIONS (CONTINUED) Num Pins Name Symbol Buffer Type Description |
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