LAN9252SLASHML datasheet(82/329 Pages) MICROCHIP

82 / 329 page

LAN9252

DS00001909A-page 82

 2015 Microchip Technology Inc.

9.5

Indexed Address Mode

In Indexed Address mode, access to the internal registers and memory of the device are indirectly mapped using Index

and Data registers. The desired internal address is written into the device at a particular offset. The value written is then

used as the internal address when the associate Data register address is accessed. Three Index / Data register sets

are provided allowing for multi-threaded operation without the concern of one thread corrupting the Index set by another

thread. Endianness can be configured per Index / Data pair. Another Data register is provided for access to the FIFOs.

The host address register map is given below. In 8-bit data mode, the host address input (ADDR[4:0]) is a BYTE

address. In 16-bit data mode, ADDR0 is not provided and the host address input (ADDR[4:1]) is a WORD address.

As discussed below in Section 9.5.5.1, "Index Register Bypass FIFO Access", the EtherCAT Process RAM Data FIFOs

are accessed when reading or writing at address 18h-1Bh.

TABLE 9-3:

HOST BUS INTERFACE INDEXED ADDRESS MODE REGISTER MAP

BYTE

ADDRESS

SYMBOL

00h-03h

HBI_IDX_0

Host Bus Interface Index Register 0

04h-07h

HBI_DATA_0

Host Bus Interface Data Register 0

08h-0Bh

HBI_IDX_1

Host Bus Interface Index Register 1

0Ch-0Fh

HBI_DATA_1

Host Bus Interface Data Register 1

10h-13h

HBI_IDX_2

Host Bus Interface Index Register 2

14h-17h

HBI_DATA_2

Host Bus Interface Data Register 2

18h-1Bh

PROCESS_RAM_FIFO

Process RAM Write Data FIFO

Process RAM Read Data FIFO

1Ch-1Fh

HBI_CFG

Host Bus Interface Configuration Register

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