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LAN9252/ML 数据表(PDF) 76 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 76 Page - Microchip Technology |
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76 / 329 page ![]() LAN9252 DS00001909A-page 76 2015 Microchip Technology Inc. 8-BIT WRITE The address is latched simultaneously from AD[7:0] and AD[15:8]. A write on AD[7:0] follows. AD[15:8] pins are not used or driven for the data phase as the host could potentially continue to drive the upper address on these signals. The cycle is repeated for the other BYTEs of the DWORD. 8-BIT READS AND WRITES TO CONSTANT ADDRESS The address is latched simultaneously from AD[7:0] and AD[15:8]. A mix of reads and writes on AD[7:0] follows. AD[15:8] pins are not used or driven for the data phase as the host could potentially continue to drive the upper address on these signals. FIGURE 9-17: MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 8-BIT WRITE Note: Generally, four 8-bit reads to opposite BYTEs of the same DWORD are required. 8-bit reads and writes to the same BYTE is a special case. FIGURE 9-18: MULTIPLEXED ADDRESSING WITH SINGLE PHASE LATCHING - 8-BIT READS AND WRITES CONSTANT ADDRESS ALELO ALEHI CS RD WR Address Low Data 7:0 Address+1 Low Data 15:8 Address High Address High Optional Optional Address+2 Low Data 23:16 Address High Address+3 Low Data 31:24 Address High Optional Optional AD[15:8] AD[7:0] ALELO ALEHI CS RD WR Address Low Address High Data 7:0 Optional AD[15:8] AD[7:0] Data 7:0 Data 7:0 Data 7:0 Data 7:0 |
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