LAN9252SLASHML datasheet(78/329 Pages) MICROCHIP

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LAN9252

DS00001909A-page 78

 2015 Microchip Technology Inc.

9.4.5

MULTIPLEXED ADDRESSING MODE TIMING REQUIREMENTS

The following figures and tables specify the timing requirements during Multiplexed Address / Data mode. Since timing

requirements are similar across the multitude of operations (e.g. dual vs. single phase, 8 vs. 16-bit), many timing

requirements are illustrated onto the same figures and do not necessarily represent any particular functional operation.

The following should be noted for the timing specifications in this section:

• The diagrams in this section depict active-high ALEHI/ALELO, CS, RD, WR, RD_WR and ENB signals. The

polarities of these signals are selectable via the HBI ALE Polarity, HBI Chip Select Polarity, HBI Read, Read/Write

Polarity, and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI Modes), respectively. Refer to

Section 9.3, "Control Line Polarity," on page 62 for additional details.

• Qualification of the ALELO and/or ALEHI with the CS signal is selectable via the HBI ALE Qualification bit of the

PDI Configuration Register (HBI Modes). This is shown as a dashed line. Timing requirements between ALELO /

ALEHI and CS only apply when this mode is active.

• In dual phase address latching mode, the ALEHI and ALELO cycles can be in any order. ALEHI first is depicted

in solid line. ALELO first is depicted in dashed line.

• A read cycle maybe followed by followed by an address cycle, a write cycle or another read cycle. A write cycle

maybe followed by followed by a read cycle or another write cycle. These are shown in dashed line.

9.4.5.1

Read Timing Requirements

If RD and WR signaling is used, a host read cycle begins when RD is asserted with CS active. The cycle ends when RD

is de-asserted. CS maybe asserted and de-asserted along with RD but not during RD active.

Alternatively, if RD_WR and ENB signaling is used, a host read cycle begins when ENB is asserted with CS active and

RD_WR indicating a read. The cycle ends when ENB is de-asserted. CS maybe asserted and de-asserted along with

ENB but not during ENB active.

Please refer to Section 9.4.4, "Multiplexed Addressing Mode Functional Timing Diagrams," on page 68 for functional

descriptions.

FIGURE 9-21:

MULTIPLEXED ADDRESSING READ CYCLE TIMING

ALEHI

AD[7:0] input

ALELO

AD[15:8] input

ENB, RD

AD[15:8] output

AD[7:0] output

tadrs

tadrh

tcsale

talerd

trddh, tcsdh

taledv

trd

trddz, tcsdz

taleale

twale

trdrd

trdwr

trdale

trdcyc

RD_WR

trdwrs

trdwrh

tcsrd

trdcs

trddv, tcsdv

trdon, tcson

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