LAN9252SLASHML datasheet(8/329 Pages) MICROCHIP

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LAN9252

DS00001909A-page 8

 2015 Microchip Technology Inc.

2.0

GENERAL DESCRIPTION

The LAN9252 is a 2/3-port EtherCAT slave controller with dual integrated Ethernet PHYs which each contain a full-

duplex 100BASE-TX transceiver and support 100Mbps (100BASE-TX) operation. The LAN9252 supports HP Auto-

MDIX, allowing the use of direct connect or cross-over LAN cables. 100BASE-FX is supported via an external fiber

transceiver.

The LAN9252 includes an EtherCAT slave controller with 4K bytes of Dual Port memory (DPRAM) and 3 Fieldbus Mem-

ory Management Units (FMMUs). Each FMMU performs the task of mapping logical addresses to physical addresses.

The EtherCAT slave controller also includes 4 SyncManagers to allow the exchange of data between the EtherCAT mas-

ter and the local application. Each SyncManager's direction and mode of operation is configured by the EtherCAT mas-

ter. Two modes of operation are available: buffered mode or mailbox mode. In the buffered mode, both the local

microcontroller and EtherCAT master can write to the device concurrently. The buffer within the LAN9252 will always

contain the latest data. If newer data arrives before the old data can be read out, the old data will be dropped. In mailbox

mode, access to the buffer by the local microcontroller and the EtherCAT master is performed using handshakes, guar-

anteeing that no data will be dropped.

Two user selectable host bus interface options are available:

• Indexed register access

This implementation provides three index/data register banks, each with independent Byte/WORD to DWORD

conversion. Internal registers are accessed by first writing one of the three index registers, followed by reading or

writing the corresponding data register. Three index/data register banks support up to 3 independent driver

threads without access conflicts. Each thread can write its assigned index register without the issue of another

thread overwriting it. Two 16-bit cycles or four 8-bit cycles are required within the same 32-bit index/data register -

however, these access can be interleaved. Direct (non-indexed) read and write accesses are supported to the

process data FIFOs. The direct FIFO access provides independent Byte/WORD to DWORD conversion, support-

ing interleaved accesses with the index/data registers.

• Multiplexed address/data bus

This implementation provides a multiplexed address and data bus with both single phase and dual phase address

support. The address is loaded with an address strobe followed by data access using a read or write strobe. Two

back to back 16-bit data cycles or 4 back to back 8-bit data cycles are required within the same 32-bit DWORD.

These accesses must be sequential without any interleaved accesses to other registers. Burst read and write

accesses are supported to the process data FIFOs by performing one address cycle followed by multiple read or

write data cycles.

The HBI supports 8/16-bit operation with big, little, and mixed endian operations. Two process data RAM FIFOs inter-

face the HBI to the EtherCAT slave controller and facilitate the transferring of process data information between the host

CPU and the EtherCAT slave. A configurable host interrupt pin allows the device to inform the host CPU of any internal

interrupts.

An SPI / Quad SPI slave controller provides a low pin count synchronous slave interface that facilitates communication

between the device and a host system. The SPI / Quad SPI slave allows access to the System CSRs, internal FIFOs

and memories. It supports single and multiple register read and write commands with incrementing, decrementing and

static addressing. Single, Dual and Quad bit lanes are supported with a clock rate of up to 80 MHz.

The LAN9252 supports numerous power management and wakeup features. The LAN9252 can be placed in a reduced

power mode and can be programmed to issue an external wake signal (IRQ) via several methods, including “Magic

Packet”, “Wake on LAN”, wake on broadcast, wake on perfect DA, and “Link Status Change”. This signal is ideal for

triggering system power-up using remote Ethernet wakeup events. The device can be removed from the low power state

via a host processor command or one of the wake events.

For simple digital modules without microcontrollers, the LAN9252 can also operate in Digital I/O Mode where 16 digital

signals can be controlled or monitored by the EtherCAT master.

To enable star or tree network topologies, the device can be configured as a 3-port slave, providing an additional MII

port. This port can be connected to an external PHY, forming a tap along the current daisy chain, or to another LAN9252

creating a 4-port solution. The MII port can point upstream (as Port 0) or downstream (as Port 2).

LED support consists of a standard RUN indicator and a LINK / Activity indicator per port. A 64-bit distributed clock is

included to enable high-precision synchronization and to provide accurate information about the local timing of data

acquisition.

The LAN9252 can be configured to operate via a single 3.3V supply utilizing an integrated 3.3V to 1.2V linear regulator.

The linear regulator may be optionally disabled, allowing usage of a high efficiency external regulator for lower system

power dissipation.

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