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LAN9252/ML 数据表(PDF) 48 Page - Microchip Technology

部件名 LAN9252/ML
功能描述  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

LAN9252/ML 数据表(HTML) 48 Page - Microchip Technology

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LAN9252
DS00001909A-page 48
 2015 Microchip Technology Inc.
27
Power Management Wakeup (PM_WAKE)
When set, this bit enables automatic wake-up based on PME events.
0: Manual Wakeup only
1: Auto Wakeup enabled
R/W
0b
26
LED Disable (LED_DIS)
This bit disables LED outputs. Open-drain / open-source LEDs are un-driven.
Push-pull LEDs are still driven but are set to their inactive state.
0: LEDs are enabled
1: LEDs are disabled
R/W
0b
25:22
RESERVED
RO
-
21
EtherCAT Core Clock Disable (ECAT_DIS)
This bit disables the clocks for the EtherCAT core.
0: Clocks are enabled
1: Clocks are disabled
In order for this bit to be set, it must be written as a 1 two consecutive times.
A write of a 0 will reset the count.
R/W
0b
20
RESERVED
RO
-
19:18
RESERVED
RO
-
17
Energy-Detect / WoL Status Port B (ED_WOL_STS_B)
This bit indicates an energy detect or WoL event occurred on the Port B PHY.
In order to clear this bit, it is required that the event in the PHY be cleared as
well. The event sources are described in Section 6.3, "Power Management,"
on page 43.
R/WC
0b
16
Energy-Detect / WoL Status Port A (ED_WOL_STS_A)
This bit indicates an energy detect or WoL event occurred on the Port A PHY.
In order to clear this bit, it is required that the event in the PHY be cleared as
well. The event sources are described in Section 6.3, "Power Management,"
on page 43.
R/WC
0b
15
Energy-Detect / WoL Enable Port B (ED_WOL_EN_B)
When set, the PME_INT bit in the Interrupt Status Register (INT_STS) will be
asserted upon an energy-detect or WoL event from Port B.
R/W
0b
14
Energy-Detect / WoL Enable Port A (ED_WOL_EN_A)
When set, the PME_INT bit in the Interrupt Status Register (INT_STS) will be
asserted upon an energy-detect or WoL event from Port A.
R/W
0b
13:10
RESERVED
RO
-
9
RESERVED
RO
-
8:7
RESERVED
RO
-
6:5
RESERVED
RO
-
Bits
Description
Type
Default



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