LAN9252SLASHML datasheet(90/329 Pages) MICROCHIP

90 / 329 page

LAN9252

DS00001909A-page 90

 2015 Microchip Technology Inc.

9.5.5

ETHERCAT PROCESS RAM DATA FIFO ACCESS

9.5.5.1

Index Register Bypass FIFO Access

In addition to the indexed access, the Index Registers can be bypassed and the FIFOs accessed at address 18h-1Bh.

At this address, host write operations are to the EtherCAT Process RAM Write Data FIFO and host read operations are

from EtherCAT Process RAM Read Data FIFO. There is no associated Index Register.

The endianness of FIFO accesses using this method is specified by the FIFO Endianness bit in the Host Bus Interface

Configuration Register.

9.5.6

INDEXED ADDRESS MODE FUNCTIONAL TIMING DIAGRAMS

The following timing diagrams illustrate example indexed (non-multiplexed) addressing mode read and write cycles for

various configurations and bus sizes. These diagrams do not cover every supported host bus permutation, but are

selected to detail the main configuration differences (bus size, Configuration/Index/Data/FIFO-Direct cycles) within the

indexed addressing mode of operation.

The following should be noted for the timing diagrams in this section:

• The diagrams in this section depict active-high CS, RD, and WR signals. The polarities of these signals are select-

able via the HBI Chip Select Polarity, HBI Read, Read/Write Polarity, and HBI Write, Enable Polarity bits of the

PDI Configuration Register (HBI Modes), respectively. Refer to Section 9.3, "Control Line Polarity," on page 62 for

additional details.

• The diagrams in this section depict little endian byte ordering. However, configurable big and little endianess are

supported via the endianness bits in the Host Bus Interface Configuration Register. Endianess changes only the

order of the bytes involved, and not the overall timing requirements. Refer to Section 9.5.4.3, "Host Endianness,"

on page 87 for additional information.

• The diagrams in this section utilize RD and WR signals. Alternative RD_WR and ENB signaling is also supported,

similar to the multiplexed example in Section 9.4.4.3, "RD_WR / ENB Control Mode Examples". The HBI read/

write mode is selectable via the HBI Read/Write Mode bit of the PDI Configuration Register (HBI Modes). The

polarities of the RD_WR and ENB signals are selectable via the HBI Read, Read/Write Polarity, and HBI Write,

Enable Polarity bits of the PDI Configuration Register (HBI Modes).

• When accessing internal registers or FIFOs in 16 and 8-bit modes, consecutive address cycles must be within the

same DWORD until the DWORD is completely accessed (some internal registers are excluded from this require-

ment). Although BYTEs and WORDs can be accessed in any order, the diagrams in this section depict accessing

the lower address BYTE or WORD first.

9.5.6.1

Configuration Register Data Access

The figures in this section detail configuration register read and write operations in indexed address mode for 16 and 8-

bit modes.

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