LAN9252SLASHML datasheet(36/329 Pages) MICROCHIP

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LAN9252

DS00001909A-page 36

 2015 Microchip Technology Inc.

5.2.2

BACK-TO-BACK READ CYCLES

There are also restrictions on specific back-to-back host read operations. These restrictions concern reading specific

registers after reading a resource that has side effects. In many cases there is a delay between reading the device, and

the subsequent indication of the expected change in the control and status register values.

In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have been estab-

lished. These periods are specified in Table 5-3. The host processor is required to wait the specified period of time

between read operations of specific combinations of resources. The wait period is dependent upon the combination of

registers being read.

Performing “dummy” reads of the Byte Order Test Register (BYTE_TEST) register is a convenient way to guarantee that

the minimum wait time restriction is met. Table 5-3 below also shows the number of dummy reads that are required for

back-to-back read operations. The number of BYTE_TEST reads in this table is based on the minimum timing for Tcyc

(45ns). For microprocessors with slower busses the number of reads may be reduced as long as the total time is equal

to, or greater than the time specified in the table. Dummy reads of the BYTE_TEST register are not required as long as

the minimum time period is met.

Note that depending on the host interface mode in use, the basic host interface cycle may naturally provide sufficient

time between reads. It is required of the system design and register access mechanisms to ensure the proper timing.

For example, multiple reads to the same register may occur faster than reads to different registers.

For 8 and 16-bit read cycles, the wait time for the back-to-back read operation is required only after the reading of the

last BYTE or WORD of the register, which completes a single DWORD transfer. There is no wait requirement between

the BYTE or WORD accesses within the DWORD transfer.

General Purpose Timer Con-

figuration Register

(GPT_CFG)

General Purpose Timer Con-

figuration Register

(GPT_CFG)

170

General Purpose Timer Count

EtherCAT Process RAM Write

Data FIFO

(ECAT_PRAM_WR_DATA)

EtherCAT Process RAM Write

Command Register

(ECAT_PRAM_WR_CMD)

TABLE 5-3:

READ AFTER READ TIMING RULES

After reading...

wait for this many

nanoseconds...

or Perform this many

Reads of BYTE_TEST…

(assuming Tcyc of 45ns)

before reading...

EtherCAT Process RAM Read

Data FIFO

(ECAT_PRAM_RD_DATA)

EtherCAT Process RAM Read

Command Register

(ECAT_PRAM_RD_CMD)

TABLE 5-2:

READ AFTER WRITE TIMING RULES (CONTINUED)

After Writing...

wait for this many

nanoseconds...

or Perform this many

Reads of BYTE_TEST…

(assuming Tcyc of 45ns)

before reading...

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