LAN9252SLASHML datasheet(63/329 Pages) MICROCHIP

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DS00001909A-page 63

LAN9252

Qualification of the ALELO signal with the CS signal is selectable. When qualification is enabled, CS must be active

during ALELO in order to strobe the address inputs. When qualification is not enabled, CS is a don’t care during the

address phase.

The address is retained for all future read and write operations. It is retained until either a reset event occurs or a new

address is loaded. This allows multiple read and write requests to take place to the same address, without requiring

multiple address latching operations.

9.4.1.2

Dual Phase Address Latching

In Dual Phase mode, the lower 8 address bits are strobed into the device using the inactive going edge of the ALELO

signal and the remaining upper address bits, the FIFO Direct Select signals and the endianness select are strobed into

the device using the trailing edge of the ALEHI signal. The strobes can be in either order. In 8-bit data mode, pins

AD[15:8] are not used. In 16-bit data mode, pins D[15:8] are used only for data.

Qualification of the ALELO and ALEHI signals with the CS signal is selectable. When qualification is enabled, CS must

be active during ALELO and ALEHI in order to strobe the address inputs. When qualification is not enabled, CS is a

don’t care during the address phase.

The address is retained for all future read and write operations. It is retained until either a reset event occurs or a new

address is loaded. This allows multiple read and write requests to take place to the same address, without requiring

multiple address latching operations.

9.4.1.3

Address Bit to Address / Data Pin Mapping

In 8-bit data mode, address bit 0 is multiplexed onto pin AD[0], address bit 1 onto pin AD[1], etc. The highest address

bit is bit 9 and is multiplexed onto pin AD[9] (single phase) or AD[1] (dual phase). The address latched into the device

is considered a BYTE address and covers 1K bytes (0 to 3FFh).

In 16-bit data mode, address bit 1 is multiplexed onto pin AD[0], address bit 2 onto pin AD[1], etc. The highest address

bit is bit 9 and is multiplexed onto pin AD[8] (single phase) or AD[0] (dual phase). The address latched into the device

is considered a WORD address and covers 512 words (0 to 1FFh).

When the address is sent to the rest of the device, it is converted to a BYTE address.

9.4.1.4

Endianness Select to Address / Data Pin Mapping

The endianness select is included into the multiplexed address to allow the host system to dynamically select the endi-

anness based on the memory address used. This allows for mixed endian access for registers and memory.

The endianness selection is multiplexed to the data pin one bit above the last address bit.

9.4.1.5

FIFO Direct Select to Address / Data Pin Mapping

The FIFO Direct Select signal is included into the multiplexed address to allow the host system to address the EtherCAT

Process RAM Data FIFOs as if they were a large flat address space.

The FIFO Direct Select signal is multiplexed to the data pin two bits above the last address bit.

9.4.2

DATA CYCLES

The host data bus can be 16 or 8-bits wide while all internal registers are 32 bits wide. The Host Bus Interface performs

the conversion from WORDs or BYTEs to DWORD, while in 8 or 16-bit data mode. Two or four contiguous accesses

within the same DWORD are required in order to perform a write or read.

9.4.2.1

Write Cycles

A write cycle occurs when CS and WR are active (or when ENB is active with RD_WR indicating write). The host address

and endianness were already captured during the address latch cycle.

On the trailing edge of the write cycle (either WR or CS or ENB going inactive), the host data is captured into registers

in the HBI. Depending on the bus width, either a WORD or a BYTE is captured. For 8 or 16-bit data modes, this functions

as the DWORD assembly with the affected WORD or BYTE determined by the lower address inputs. BYTE swapping

is also done at this point based on the endianness.

WRITES FOLLOWING INITIALIZATION

Following device initialization, writes from the Host Bus are ignored until after a read cycle is performed.

WRITES DURING AND FOLLOWING POWER MANAGEMENT

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