LAN9252SLASHML datasheet(34/329 Pages) MICROCHIP

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LAN9252

DS00001909A-page 34

 2015 Microchip Technology Inc.

5.1

System Control and Status Registers

The System CSRs are directly addressable memory mapped registers with a base address offset range of 050h to 314h.

These registers are addressable by the Host via the Host Bus Interface (HBI) or SPI/SQI. For more information on the

various device modes and their corresponding address configurations, see Section 2.0, "General Description," on

page 8.

Table 5-1 lists the System CSRs and their corresponding addresses in order. All system CSRs are reset to their default

value on the assertion of a chip-level reset.

The System CSRs can be divided into the following sub-categories. Each of these sub-categories is located in the cor-

responding chapter and contains the System CSR descriptions of the associated registers. The register descriptions

are categorized as follows:

• Section 6.2.3, "Reset Registers," on page 42

• Section 6.3.5, "Power Management Registers," on page 47

• Section 8.3, "Interrupt Registers," on page 56

• Section 12.13, "EtherCAT CSR and Process Data RAM Access Registers (Directly Addressable)," on page 214

• Section 16.1, "Miscellaneous System Configuration & Status Registers," on page 301

Note:

Unlisted registers are reserved for future use.

TABLE 5-1:

SYSTEM CONTROL AND STATUS REGISTERS

Address

000h-01Ch

EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA)

020h-03Ch

EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA)

050h

Chip ID and Revision (ID_REV)

054h

Interrupt Configuration Register (IRQ_CFG)

058h

Interrupt Status Register (INT_STS)

05Ch

Interrupt Enable Register (INT_EN)

064h

Byte Order Test Register (BYTE_TEST)

074h

Hardware Configuration Register (HW_CFG)

084h

Power Management Control Register (PMT_CTRL)

08Ch

General Purpose Timer Configuration Register (GPT_CFG)

090h

General Purpose Timer Count Register (GPT_CNT)

09Ch

Free Running 25MHz Counter Register (FREE_RUN)

Reset Register

1F8h

Reset Control Register (RESET_CTL)

EtherCAT Registers

300h

EtherCAT CSR Interface Data Register (ECAT_CSR_DATA)

304h

EtherCAT CSR Interface Command Register (ECAT_CSR_CMD)

308h

EtherCAT Process RAM Read Address and Length Register (ECAT_PRAM_RD_ADDR_LEN)

30Ch

EtherCAT Process RAM Read Command Register (ECAT_PRAM_RD_CMD)

310h

EtherCAT Process RAM Write Address and Length Register (ECAT_PRAM_WR_ADDR_LEN)

314h

EtherCAT Process RAM Write Command Register (ECAT_PRAM_WR_CMD)

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