LAN9252SLASHML datasheet(83/329 Pages) MICROCHIP

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DS00001909A-page 83

LAN9252

9.5.1

HOST BUS INTERFACE INDEX REGISTER

The Index registers are writable as WORDs or as BYTEs, depending upon the data mode. There is no concern about

DWORD assembly rules when writing these registers. The Index registers are formatted as follows:

Note 13:

The default may be used to help determine the endianness of the register.

9.5.2

HOST BUS INTERFACE CONFIGURATION REGISTER

The HBI Configuration register is used to specify the endianness of the interface. Endianess for each Index / Data pair

and for FIFO accesses can be individually specified.

The endianness of this register is irrelevant since each byte is shadowed into 4 positions.

The HBI Configuration register is writable as WORDs or as BYTEs, depending upon the data mode. There is no concern

about DWORD assembly rules when writing this register. The Configuration register is formatted as follows:

Bits

Description

Type

Default

31:16

RESERVED

15:0

Internal Address

The address used when the corresponding Data register is accessed.

Note:

The internal address provided by each Index register is always

considered to be a BYTE address.

R/W

1234h

Note 13

Bits

Description

Type

Default

31:28

RESERVED

FIFO Endianness Shadow 3

This bit is a shadow of bit 3.

R/W

Host Bus Interface Index / Data Register 2 Endianness Shadow 3

This bit is a shadow of bit 2.

R/W

Host Bus Interface Index / Data Register 1 Endianness Shadow 3

This bit is a shadow of bit 1.

R/W

Host Bus Interface Index / Data Register 0 Endianness Shadow 3

This bit is a shadow of bit 0.

R/W

23:20

RESERVED

FIFO Endianness Shadow 2

This bit is a shadow of bit 3.

R/W

Host Bus Interface Index / Data Register 2 Endianness Shadow 2

This bit is a shadow of bit 2.

R/W

Host Bus Interface Index / Data Register 1 Endianness Shadow 2

This bit is a shadow of bit 1.

R/W

Host Bus Interface Index / Data Register 0 Endianness Shadow 2

This bit is a shadow of bit 0.

R/W

15:12

RESERVED

FIFO Endianness Shadow 1

This bit is a shadow of bit 3.

R/W

Host Bus Interface Index / Data Register 2 Endianness Shadow 1

This bit is a shadow of bit 2.

R/W

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