LAN9252SLASHML datasheet(47/329 Pages) MICROCHIP

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DS00001909A-page 47

LAN9252

6.3.5

POWER MANAGEMENT REGISTERS

6.3.5.1

Power Management Control Register (PMT_CTRL)

This read-write register controls the power management features of the device. The ready state of the device be deter-

mined via the Device Ready (READY) bit of this register.

Offset:

084h

Size:

32 bits

Note:

This register can be read while the device is in the reset or not ready / power savings states without leaving

the host interface in an intermediate state. If the host interface is in a reset state, returned data may be

invalid.

It is not necessary to read all four bytes of this register. DWORD access rules do not apply to this register.

Bits

Description

Type

Default

31:29

Power Management Mode (PM_MODE)

This register field determines the chip level power management mode that

will be entered when the Power Management Sleep Enable

(PM_SLEEP_EN) bit is set.

000: D0

001: D1

010: D2

011: D3

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Writes to this field are ignored if Power Management Sleep Enable

(PM_SLEEP_EN) is also being written with a 1.

This field is cleared when the device wakes up.

R/W/SC

000b

Power Management Sleep Enable (PM_SLEEP_EN)

Setting this bit enters the chip level power management mode specified with

the Power Management Mode (PM_MODE) field.

0: Device is not in a low power sleep state

1: Device is in a low power sleep state

This bit can not be written at the same time as the PM_MODE register field.

The PM_MODE field must be set, and then this bit must be set for proper

device operation.

Writes to this bit with a value of 1 are ignored if Power Management Mode

(PM_MODE) is being written with a new value.

Note:

Although not prevented by H/W, this bit should not be written with

a value of 1 while Power Management Mode (PM_MODE) has a

value of “D0”.

This field is cleared when the device wakes up.

R/W/SC

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