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LAN9252/ML 数据表(PDF) 20 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 20 Page - Microchip Technology |
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20 / 329 page  LAN9252 DS00001909A-page 20 2015 Microchip Technology Inc. Note 5: Refer to Section 4.0, "Power Connections," on page 29, the device reference schematics, and the device LANCheck schematic checklist for additional connection information. TABLE 3-5: LAN PORT A & B POWER AND COMMON PIN DESCRIPTIONS Num Pins Name Symbol Buffer Type Description 1 Bias Reference RBIAS AI Used for internal bias circuits. Connect to an exter- nal 12.1 kΩ, 1% resistor to ground. Refer to the device reference schematic for connec- tion information. Note: The nominal voltage is 1.2 V and the resistor will dissipate approximately 1 mW of power. 1 Port A and B FX-LOS Enable Strap FXLOSEN AI Port A and B FX-LOS Enable. This 3 level strap input selects between FX-LOS and FX-SD / copper twisted pair mode. A level below 1 V (typ.) selects FX-SD / copper twisted pair for ports A and B, further determined by FXSDENA and FXSDENB. A level of 1.5 V selects FX-LOS for port A and FX- SD / copper twisted pair for port B, further deter- mined by FXSDENB. A level above 2 V (typ.) selects FX-LOS for ports A and B. 1 +3.3 V Port A Analog Power Supply VDD33TXRX1 P See Note 5. 1 +3.3 V Port B Analog Power Supply VDD33TXRX2 P See Note 5. 1 +3.3 V Master Bias Power Supply VDD33BIAS P See Note 5. 1 Port A Transmitter +1.2 V Power Supply VDD12TX1 P This pin is supplied from either an external 1.2 V supply or from the device’s internal regulator via the PCB. This pin must be tied to the VDD12TX2 pin for proper operation. See Note 5. 1 Port B Transmitter +1.2 V Power Supply VDD12TX2 P This pin is supplied from either an external 1.2 V supply or from the device’s internal regulator via the PCB. This pin must be tied to the VDD12TX1 pin for proper operation. See Note 5. |
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