LAN9252SLASHML datasheet(43/329 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001909A-page 43

LAN9252

6.3

Power Management

The device supports several block and chip level power management features as well as wake-up event detection and

notification.

6.3.1

WAKE-UP EVENT DETECTION

6.3.1.1

PHY A & B Energy Detect

Energy Detect Power Down mode reduces PHY power consumption. In energy-detect power-down mode, the PHY will

resume from power-down when energy is seen on the cable (typically from link pulses) and set the ENERGYON inter-

rupt bit in the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x).

Refer to Section 11.2.8.2, "Energy Detect Power-Down," on page 131 for details on the operation and configuration of

the PHY energy-detect power-down mode.

If enabled, via the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x), the PHY will generate an interrupt.

This interrupt is reflected in the Interrupt Status Register (INT_STS), bit 26 (PHY_INT_A) for PHY A and bit 27

(PHY_INT_B) for PHY B. The INT_STS register bits will trigger the IRQ interrupt output pin if enabled, as described in

Section 8.2.1, "Ethernet PHY Interrupts," on page 54.

The energy-detect PHY interrupts will also set the appropriate Energy-Detect / WoL Status Port A (ED_WOL_STS_A)

or Energy-Detect / WoL Status Port B (ED_WOL_STS_B) bit of the Power Management Control Register (PMT_CTRL).

The Energy-Detect / WoL Enable Port A (ED_WOL_EN_A) and Energy-Detect / WoL Enable Port B (ED_WOL_EN_B)

bits will enable the corresponding status bits as a PME event.

6.3.1.2

PHY A & B Wake on LAN (WoL)

PHY A and B provide WoL event detection of Perfect DA, Broadcast, Magic Packet, and Wakeup frames.

When enabled, the PHY will detect WoL events and set the WoL interrupt bit in the PHY x Interrupt Source Flags Reg-

ister (PHY_INTERRUPT_SOURCE_x). If enabled via the PHY x Interrupt Mask Register (PHY_INTER-

RUPT_MASK_x), the PHY will generate an interrupt. This interrupt is reflected in the Interrupt Status Register

(INT_STS), bit 26 (PHY_INT_A) for PHY A and bit 27 (PHY_INT_B) for PHY B. The INT_STS register bits will trigger

the IRQ interrupt output pin if enabled, as described in Section 8.2.1, "Ethernet PHY Interrupts," on page 54.

Refer to Section 11.2.9, "Wake on LAN (WoL)," on page 132 for details on the operation and configuration of the PHY

WoL.

The WoL PHY interrupts will also set the appropriate Energy-Detect / WoL Status Port A (ED_WOL_STS_A) or Energy-

Detect / WoL Status Port B (ED_WOL_STS_B) bit of the Power Management Control Register (PMT_CTRL). The

Energy-Detect / WoL Enable Port A (ED_WOL_EN_A) and Energy-Detect / WoL Enable Port B (ED_WOL_EN_B) bits

enable the corresponding status bits as a PME event.

6.3.2

WAKE-UP (PME) NOTIFICATION

A simplified diagram of the logic that controls the PME interrupt can be seen in Figure 6-1.

The PME module handles the latching of the PHY B Energy-Detect / WoL Status Port B (ED_WOL_STS_B) bit and the

PHY A Energy-Detect / WoL Status Port A (ED_WOL_STS_A) bit in the Power Management Control Register (PMT_C-

TRL).

Note:

If a carrier is present when Energy Detect Power Down is enabled, then detection will occur immediately.

Note:

Any PHY interrupt will set the above status bits. The Host should only enable the appropriate PHY interrupt

source in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x).

Note:

Any PHY interrupt will set the above status bits. The Host should only enable the appropriate PHY interrupt

source in the PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x).

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