LAN9252SLASHML datasheet(42/329 Pages) MICROCHIP

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LAN9252

DS00001909A-page 42

 2015 Microchip Technology Inc.

6.2.3

RESET REGISTERS

6.2.3.1

Reset Control Register (RESET_CTL)

This register contains software controlled resets.

Offset:

1F8h

Size:

32 bits

Note:

This register can be read while the device is in the reset or not ready / power savings states without leaving

the host interface in an intermediate state. If the host interface is in a reset state, returned data may be

invalid.

It is not necessary to read all four bytes of this register. DWORD access rules do not apply to this register.

Bits

Description

Type

Default

31:7

RESERVED

EtherCAT Reset (ETHERCAT_RST)

Setting this bit resets the EtherCAT core. When the EtherCAT core is

released from reset, this bit is automatically cleared. All writes to this bit are

ignored while this bit is set.

R/W

RESERVED

Port B PHY Reset (PHY_B_RST)

Setting this bit resets the Port B PHY. The internal logic automatically holds

the PHY reset for a minimum of 102uS. When the Port B PHY is released

from reset, this bit is automatically cleared. All writes to this bit are ignored

while this bit is set.

R/W

Port A PHY Reset (PHY_A_RST)

Setting this bit resets the Port A PHY. The internal logic automatically holds

the PHY reset for a minimum of 102uS. When the Port A PHY is released

from reset, this bit is automatically cleared. All writes to this bit are ignored

while this bit is set.

R/W

Digital Reset (DIGITAL_RST)

Setting this bit resets the complete chip except the PLL, Port B PHY and Port

A PHY. All system CSRs are reset except for any NASR type bits.

When the chip is released from reset, this bit is automatically cleared. All

writes to this bit are ignored while this bit is set.

R/W

LAN9252/ML 数据表(PDF) 42 Page - Microchip Technology

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