LAN9252SLASHML datasheet(44/329 Pages) MICROCHIP

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LAN9252

DS00001909A-page 44

 2015 Microchip Technology Inc.

This module also masks the status bits with the corresponding enable bits (Energy-Detect / WoL Enable Port B

(ED_WOL_EN_B) and Energy-Detect / WoL Enable Port A (ED_WOL_EN_A)) and combines the results together to

generate the Power Management Interrupt Event (PME_INT) status bit in the Interrupt Status Register (INT_STS). The

PME_INT status bit is then masked with the Power Management Event Interrupt Enable (PME_INT_EN) bit and com-

bined with the other interrupt sources to drive the IRQ output pin.

When the PM_WAKE bit of the Power Management Control Register (PMT_CTRL) is set, the PME event will automat-

ically wake up the system in certain chip level power modes, as described in Section 6.3.4.2, "Exiting Low Power

Modes," on page 46.

6.3.3

BLOCK LEVEL POWER MANAGEMENT

The device supports software controlled clock disabling of various modules in order to reduce power consumption.

6.3.3.1

Disabling The EtherCAT Core

The entire EtherCAT Core may be disabled by setting the ECAT_DIS bit in the Power Management Control Register

(PMT_CTRL). As a safety precaution, in order for this bit to be set, it must be written as a 1 two consecutive times. A

write of a 0 will reset the count.

Note:

The PME interrupt status bit (PME_INT) in the INT_STS register is set regardless of the setting of

PME_INT_EN.

FIGURE 6-1:

PME INTERRUPT SIGNAL GENERATION

Note:

Disabling individual blocks does not automatically reset the block, it only places it into a static non-opera-

tional state in order to reduce the power consumption of the device. If a block reset is not performed before

re-enabling the block, then care must be taken to ensure that the block is in a state where it can be disabled

and then re-enabled.

ED_WOL_EN_A (bit

14) of PMT_CTRL

Denotes a level-triggered "sticky" status bit

PME_INT_EN (bit 17)

of INT_EN register

PME_INT (bit 17)

of INT_STS register

IRQ_EN (bit 8)

of IRQ_CFG register

IRQ

Other System

Interrupts

ED_WOL_STS_A (bit 16)

of PMT_CTRL register

INT7_MASK (bit 7) of

PHY_INTERRUPT_MASK_A register

INT7 (bit 7) of

PHY_INTERRUPT_SOURCE_A register

Polarity &

Buffer Type

Logic

INT8_MASK (bit 8) of

PHY_INTERRUPT_MASK_A register

INT8 (bit 8) of

PHY_INTERRUPT_SOURCE_A register

ED_WOL_EN_B (bit

15) of PMT_CTRL

ED_WOL_STS_B (bit 17)

of PMT_CTRL register

INT7_MASK (bit 7) of

PHY_INTERRUPT_MASK_B register

INT7 (bit 7) of

PHY_INTERRUPT_SOURCE_B register

INT8_MASK (bit 8) of

PHY_INTERRUPT_MASK_B register

INT8 (bit 8) of

PHY_INTERRUPT_SOURCE_B register

Other PHY Interrupts

PM_WAKE (bit 28) of

PMT_CTRL register

PME wake-up

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