LAN9252SLASHML datasheet(64/329 Pages) MICROCHIP

64 / 329 page

LAN9252

DS00001909A-page 64

 2015 Microchip Technology Inc.

During and following any power management mode other than D0, writes from the Host Bus are ignored until after a

read cycle is performed.

8 AND 16-BIT ACCESS

While in 8 or 16-bit data mode, the host is required to perform two or four, 16 or 8-bit writes to complete a single DWORD

transfer. No ordering requirements exist. The host can access either the low or high WORD or BYTE first, as long as

the other write(s) is(are) performed to the remaining WORD or BYTEs.

A write BYTE / WORD counter keeps track of the number of writes. At the trailing edge of the write cycle, the counter is

incremented. Once all writes occur, a 32-bit write is performed to the internal register.

The write BYTE / WORD counter is reset if the power management mode is set to anything other than D0.

9.4.2.2

Read Cycles

A read cycle occurs when CS and RD are active (or when ENB is active with RD_WR indicating read). The host address

and endianness were already captured during the address latch cycle.

At the beginning of the read cycle, the appropriate register is selected and its data is driven onto the data pins. Depend-

ing on the bus width, either a WORD or a BYTE is read. For 8 or 16-bit data modes, the returned BYTE or WORD is

determined by the endianness and the lower address inputs.

POLLING FOR INITIALIZATION COMPLETE

Before device initialization, the HBI will not return valid data. To determine when the HBI is functional, the Byte Order

Test Register (BYTE_TEST) should be polled. Each poll should consist of an address latch cycle(s) and a data cycle.

Once the correct pattern is read, the interface can be considered functional. At this point, the Device Ready (READY)

bit in the Hardware Configuration Register (HW_CFG) can be polled to determine when the device is fully configured.

READS DURING AND FOLLOWING POWER MANAGEMENT

During any power management mode other than D0, reads from the Host Bus are ignored. If the power management

mode changes back to D0 during an active read cycle, the tail end of the read cycle is ignored. Internal registers are not

affected and the state of the HBI does not change.

8 AND 16-BIT ACCESS

For certain register accesses, the host is required to perform two or four consecutive 16 or 8-bit reads to complete a

single DWORD transfer. No ordering requirements exist. The host can access either the low or high WORD or BYTE

first, as long as the other read(s) is(are) performed from the remaining WORD or BYTEs.

A read BYTE / WORD counter keeps track of the number of reads. This counter is separate from the write counter

above. At the trailing edge of the read cycle, the counter is incremented. On the last read for the DWORD, an internal

read is performed to update any Change on Read CSRs.

The read BYTE / WORD counter is reset if the power management mode is set to anything other than D0.

SPECIAL CSR HANDLING

Live Bits

Any register bit that is updated by a H/W event is held at the beginning of the read cycle to prevent it from changing

during the read cycle.

Multiple BYTE / WORD Live Registers in 16 or 8-Bit Modes

Some registers have “live” fields or related fields that span across multiple BYTEs or WORDs. For 16 and 8-bit data

reads, it is possible for the value of these fields to change between host read cycles. In order to prevent reading inter-

mediate values, these registers are locked when the first byte or word is read and unlocked when the last byte or word

is read.

The registers are unlocked if the power management mode is set to anything other than D0.

Note:

Writing the same WORD or BYTEs in the same DWORD assemble cycle may cause undefined or unde-

sirable operation. The HBI hardware does not protect against this operation.

Note:

Reading the same WORD or BYTEs from the same DWORD may cause undefined or undesirable opera-

tion. The HBI hardware does not protect against this operation. The HBI simply counts that four BYTEs

have been read.

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