LAN9252SLASHML datasheet(84/329 Pages) MICROCHIP

84 / 329 page

LAN9252

DS00001909A-page 84

 2015 Microchip Technology Inc.

Host Bus Interface Index / Data Register 1 Endianness Shadow 1

This bit is a shadow of bit 1.

R/W

Host Bus Interface Index / Data Register 0 Endianness Shadow 1

This bit is a shadow of bit 0.

R/W

7:4

RESERVED

FIFO Endianness

This bit specifies the endianness of FIFO accesses when they are accessed

by means other than the Index / Data Register method.

0 = Little Endian

1 = Big Endian

Note:

In order to avoid any ambiguity with the endianness of this

are set during a write, all of the bits will be set.

R/W

Host Bus Interface Index / Data Register 2 Endianness

This bit specifies the endianness of the Index and Data register set 2.

0 = Little Endian

1 = Big Endian

Note:

In order to avoid any ambiguity with the endianness of this

are set during a write, all of the bits will be set.

R/W

Host Bus Interface Index / Data Register 1 Endianness

This bit specifies the endianness of the Index and Data register set 1.

0 = Little Endian

1 = Big Endian

Note:

In order to avoid any ambiguity with the endianness of this

are set during a write, all of the bits will be set.

R/W

Host Bus Interface Index / Data Register 0 Endianness

This bit specifies the endianness of the Index and Data register set 0.

0 = Little Endian

1 = Big Endian

Note:

In order to avoid any ambiguity with the endianness of this

are set during a write, all of the bits will be set.

R/W

Bits

Description

Type

Default

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