LAN9252SLASHML datasheet(39/329 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001909A-page 39

LAN9252

6.2.1

CHIP-LEVEL RESETS

A chip-level reset event activates all internal resets, effectively resetting the entire device. A chip-level reset is initiated

by assertion of any of the following input events:

• Power-On Reset (POR)

• RST# Pin Reset

• EtherCAT System Reset

Chip-level reset/configuration completion can be determined by first polling the Byte Order Test Register (BYTE_TEST).

The returned data will be invalid until the Host interface resets are complete. Once the returned data is the correct byte

ordering value, the Host interface resets have completed.

The completion of the entire chip-level reset must be determined by polling the READY bit of the Hardware Configura-

tion Register (HW_CFG) or Power Management Control Register (PMT_CTRL) until it is set. When set, the READY bit

indicates that the reset has completed and the device is ready to be accessed.

With the exception of the Hardware Configuration Register (HW_CFG),Power Management Control Register (PMT_C-

TRL), Byte Order Test Register (BYTE_TEST), and Reset Control Register (RESET_CTL), read access to any internal

resources should not be done by S/W while the READY bit is cleared. Writes to any address are invalid until the READY

bit is set.

A chip-level reset involves tuning of the variable output level pads, latching of configuration straps and generation of the

master reset.

CONFIGURATION STRAPS LATCHING

During POR, EtherCAT reset or RST# pin reset, the latches for the straps are open. Following the release of POR, Eth-

erCAT reset or RST# pin reset, the latches for the straps are closed.

VARIABLE LEVEL I/O PAD TUNING

Following the release of the EtherCAT, POR or RST# pin resets, a 1 uS pulse (active low), is sent into the VO tuning

circuit. 2 uS later, the output pins are enabled. The 2 uS delay allows time for the variable output level pins to tune before

enabling the outputs and also provides input hold time for strap pins that are shared with output pins.

MASTER RESET AND CLOCK GENERATION RESET

Following the enabling of the output pins, the reset is synchronized to the main system clock to become the master

reset. Master reset is used to generate the local resets and to reset the clocks generation.

6.2.1.1

Power-On Reset (POR)

A power-on reset occurs whenever power is initially applied to the device or if the power is removed and reapplied to

the device. This event resets all circuitry within the device. Configuration straps are latched and EEPROM loading is

performed as a result of this reset. The POR is used to trigger the tuning of the Variable Level I/O Pads as well as a

chip-level reset.

The POR can also used as a system level reset. RST# becomes an open-drain output and is asserted for the POR time.

Its purpose is to perform a complete reset of the EtherCAT slave and/or to hold an external PHY in reset while the Eth-

erCAT core is in reset. As an open-drain output, RST is intended to be wired OR’d into the system reset.

Following valid voltage levels, a POR reset typically takes approximately 21 ms.

6.2.1.2

RST# Pin Reset

Driving the RST# input pin low initiates a chip-level reset. This event resets all circuitry within the device. Use of this

reset input is optional, but when used, it must be driven for the period of time specified in Section 18.6.3, "Reset and

Configuration Strap Timing," on page 317. Configuration straps are latched, and EEPROM loading is performed as a

result of this reset.

Note:

The Ethernet PHY should be connected to the RST# pin so that the PHY is held in reset until the EtherCAT

Slave is ready. Otherwise, the far end Link Partner would detect valid link signals from the PHY and would

“open” its port assuming that the local EtherCAT Slave was ready.

The RST# pin is not driven until all voltages are operational. External, system level solutions are necessary

if the system needs to be held in reset during power ramp-up.

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