LAN9252SLASHML datasheet(53/329 Pages) MICROCHIP

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DS00001909A-page 53

LAN9252

8.0

SYSTEM INTERRUPTS

8.1

Functional Overview

This chapter describes the system interrupt structure of the device. The device provides a multi-tier programmable inter-

rupt structure which is controlled by the System Interrupt Controller. The programmable system interrupts are generated

internally by the various device sub-modules and can be configured to generate a single external host interrupt via the

IRQ interrupt output pin. The programmable nature of the host interrupt provides the user with the ability to optimize

performance dependent upon the application requirements. The IRQ interrupt buffer type, polarity and de-assertion

interval are modifiable. The IRQ interrupt can be configured as an open-drain output to facilitate the sharing of interrupts

with other devices. All internal interrupts are maskable and capable of triggering the IRQ interrupt.

8.2

Interrupt Sources

The device is capable of generating the following interrupt types:

• Ethernet PHY Interrupts

• Power Management Interrupts

• General Purpose Timer Interrupt (GPT)

• EtherCAT Interrupt

• Software Interrupt (General Purpose)

• Device Ready Interrupt

• Clock Output Test Mode

All interrupts are accessed and configured via registers arranged into a multi-tier, branch-like structure, as shown in

Figure 8-1. At the top level of the device interrupt structure are the Interrupt Status Register (INT_STS), Interrupt Enable

The Interrupt Status Register (INT_STS) and Interrupt Enable Register (INT_EN) aggregate and enable/disable all inter-

rupts from the various device sub-modules, combining them together to create the IRQ interrupt. These registers pro-

vide direct interrupt access/configuration to the General Purpose Timer, software and device ready interrupts. These

interrupts can be monitored, enabled/disabled and cleared, directly within these two registers. In addition, event indica-

tions are provided for the EtherCAT Slave, Power Management, and Ethernet PHY interrupts. These interrupts differ in

that the interrupt sources are generated and cleared in other sub-block registers. The INT_STS register does not pro-

vide details on what specific event within the sub-module caused the interrupt and requires the software to poll an addi-

tional sub-module interrupt register (as shown in Figure 8-1) to determine the exact interrupt source and clear it. For

interrupts which involve multiple registers, only after the interrupt has been serviced and cleared at its source will it be

cleared in the INT_STS register.

The Interrupt Configuration Register (IRQ_CFG) is responsible for enabling/disabling the IRQ interrupt output pin as

well as configuring its properties. The IRQ_CFG register allows the modification of the IRQ pin buffer type, polarity and

de-assertion interval. The de-assertion timer guarantees a minimum interrupt de-assertion period for the IRQ output

and is programmable via the Interrupt De-assertion Interval (INT_DEAS) field of the Interrupt Configuration Register

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