LAN9252SLASHML datasheet(27/329 Pages) MICROCHIP

27 / 329 page

 2015 Microchip Technology Inc.

DS00001909A-page 27

LAN9252

Note 10:

Configuration strap pins are identified by an underlined symbol name. Configuration strap values are

latched on power-on reset or RST# de-assertion. Refer to Section 7.0, "Configuration Straps," on page 51

for more information.

Link / Activity

LED Port 0

LINKACTLED0

VOD12/

VOS12

This pin is the Link/Activity LED output (off=no link,

on=link without activity, blinking=link and activity) for

port 0.

This pin is configured to be open-drain/open-source

output. The choice of open-drain vs. open-source as

well as the polarity of this pin depends upon the

strap value sampled at reset.

Note:

Refer to Section 12.10, "LEDs," on

page 208 to additional information.

Chip Mode

Configuration

Strap 0

CHIP_MODE0

VIS

(PU)

This strap, along with CHIP_MODE1, configures

the value of the Chip Mode hard-strap. See

Note 10.

TABLE 3-13:

MISCELLANEOUS PIN DESCRIPTIONS

Num

Pins

Name

Symbol

Buffer

Type

Description

Interrupt Output

IRQ

VO8/VOD8

Interrupt request output. The polarity, source and

buffer type of this signal is programmable via the

Interrupt Configuration Register (IRQ_CFG). For

more information, refer to Section 8.0, "System

Interrupts," on page 53.

System Reset

Input

RST#

VIS/VOD8

(PU)

As an input, this active low signal allows external

hardware to reset the device. The device also con-

tains an internal power-on reset circuit. Thus this

signal may be left unconnected if an external hard-

ware reset is not needed. When used this signal

must adhere to the reset timing requirements as

detailed in the Section 18.0, "Operational Character-

istics," on page 307.

As an output, this signal is driven low during POR or

in response to an EtherCAT reset command

sequence from the Master Controller or Host inter-

face.

Regulator

Enable

REG_EN

When tied to 3.3 V, the internal 1.2 V regulators are

enabled.

Test Mode

TESTMODE

VIS

(PD)

This pin must be tied to VSS for proper operation.

Crystal Input

OSCI

ICLK

External 25 MHz crystal input. This signal can also

be driven by a single-ended clock oscillator. When

this method is used, OSCO should be left uncon-

nected.

Crystal Output

OSCO

OCLK

External 25 MHz crystal output.

Crystal +1.2 V

Power Supply

OSCVDD12

Supplied by the on-chip regulator unless configured

for regulator off mode via REG_EN.

Crystal Ground

OSCVSS

Crystal ground.

TABLE 3-12:

LED & CONFIGURATION STRAP PIN DESCRIPTIONS (CONTINUED)

Num

Pins

Name

Symbol

Buffer

Type

Description

LAN9252/ML 数据表(PDF) 27 Page - Microchip Technology

LAN9252/ML 数据表(HTML) 27 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载