LAN9252SLASHML datasheet(26/329 Pages) MICROCHIP

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LAN9252

DS00001909A-page 26

 2015 Microchip Technology Inc.

TABLE 3-12:

LED & CONFIGURATION STRAP PIN DESCRIPTIONS

Num

Pins

Name

Symbol

Buffer

Type

Description

Link/Activity

LED Port 2

LINKACTLED2

VOD12/

VOS12

This pin is the Link/Activity LED output (off=no link,

on=link without activity, blinking=link and activity) for

port 2.

This pin is configured to be an open-drain/open-

source output. The choice of open-drain vs. open-

source as well as the polarity of this pin depends

upon the strap value sampled at reset.

Note:

Refer to Section 12.10, "LEDs," on

page 208 to additional information.

MII Port

Link Polarity

Configuration

Strap

MII_LINKPOL

VIS

(PU)

This strap configures the polarity of the MII_LINK

pin by setting the value of link_pol_strap_mii. See

Note 10.

Run LED

RUNLED

VOD12/

VOS12

This pin is the Run LED output and is controlled by

the AL Status Register.

This pin is configured to be open-drain/open-source

output. The choice of open-drain vs. open-source as

well as the polarity of this pin depends upon the

strap value sampled at reset.

Note:

Refer to Section 12.10, "LEDs," on

page 208 to additional information.

EEPROM Size

Configuration

Strap

E2PSIZE

VIS

(PU)

This strap configures the value of the EEPROM

size hard-strap. See Note 10.

A low selects 1K bits (128 x 8) through 16K bits (2K

x 8).

A high selects 32K bits (4K x 8) through 4Mbits

(512K x 8).

Link / Activity

LED Port 1

LINKACTLED1

VOD12/

VOS12

This pin is the Link/Activity LED output (off=no link,

on=link without activity, blinking=link and activity) for

port 1.

This pin is configured to be open-drain/open-source

output. The choice of open-drain vs. open-source as

well as the polarity of this pin depends upon the

strap value sampled at reset.

Note:

Refer to Section 12.10, "LEDs," on

page 208 to additional information.

Chip Mode

Configuration

Strap 1

CHIP_MODE1

VIS

(PU)

This strap, along with CHIP_MODE0, configures

the value of the Chip Mode hard-strap. See

Note 10.

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