LAN9252SLASHML datasheet(32/329 Pages) MICROCHIP

32 / 329 page

LAN9252

DS00001909A-page 32

 2015 Microchip Technology Inc.

5.0

This chapter details the device register map and summarizes the various directly addressable System Control and Sta-

tus Registers (CSRs). Detailed descriptions of the System CSRs are provided in the chapters corresponding to their

function. Additional indirectly addressable registers are available in the various sub-blocks of the device. These regis-

ters are also detailed in their corresponding chapters.

Directly Addressable Registers

• Section 12.13, "EtherCAT CSR and Process Data RAM Access Registers (Directly Addressable)," on page 214

• Section 5.1, "System Control and Status Registers," on page 34

Indirectly Addressable Registers

• Section 11.2.16, "PHY Registers," on page 142

• Section 12.14, "EtherCAT Core CSR Registers (Indirectly Addressable)," on page 223

Figure 5-1 contains an overall base register memory map of the device. This memory map is not drawn to scale, and

should be used for general reference only. Table 5-1 provides a summary of all directly addressable CSRs and their

corresponding addresses.

Note:

Not all device registers are memory mapped or directly addressable. For details on the accessibility of the

various device registers, refer the register sub-sections listed above.

LAN9252/ML 数据表(PDF) 32 Page - Microchip Technology