LAN9252SLASHML datasheet(98/329 Pages) MICROCHIP

98 / 329 page

LAN9252

DS00001909A-page 98

 2015 Microchip Technology Inc.

9.5.7

INDEXED ADDRESSING MODE TIMING REQUIREMENTS

The following figures and tables specify the timing requirements during Indexed Address mode. Since timing require-

ments are similar across the multitude of operations (e.g. 8 vs. 16-bit, Index vs. Configuration vs. Data registers, FIFO

Direct Select), many timing requirements are illustrated in the same figures and do not necessarily represent any par-

ticular functional operation.

The following should be noted for the timing specifications in this section:

• The diagrams in this section depict active-high CS, RD, WR, RD_WR and ENB signals. The polarities of these sig-

nals are selectable via the HBI Chip Select Polarity, HBI Read, Read/Write Polarity, and HBI Write, Enable Polar-

ity bits of the PDI Configuration Register (HBI Modes), respectively. Refer to Section 9.3, "Control Line Polarity,"

on page 62 for additional details.

• A read cycle maybe followed by followed by a write cycle or another read cycle. A write cycle maybe followed by

followed by a read cycle or another write cycle. These are shown in dashed line.

9.5.7.1

Read Timing Requirements

If RD and WR signaling is used, a host read cycle begins when RD is asserted with CS active. The cycle ends when RD

is de-asserted. CS maybe asserted and de-asserted along with RD but not during RD active.

Alternatively, if RD_WR and ENB signaling is used, a host read cycle begins when ENB is asserted with CS active and

RD_WR indicating a read. The cycle ends when ENB is de-asserted. CS maybe asserted and de-asserted along with

ENB but not during ENB active.

Please refer to Section 9.5.6, "Indexed Address Mode Functional Timing Diagrams," on page 90 for functional descrip-

tions.

FIGURE 9-36:

INDEXED ADDRESSING READ CYCLE TIMING

trddv, tcsdv

A[4:0]

ENB, RD

D[15:8]

D[7:0]

trdon, tcson

trddh, tcsdh

tadv

trd

trddz, tcsdz

trdrd

trdwr

trdcyc

RD_WR

trdwrs

trdwrh

tcsrd

trdcs

tah

tas

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