LAN9252SLASHML datasheet(99/329 Pages) MICROCHIP

99 / 329 page

 2015 Microchip Technology Inc.

DS00001909A-page 99

LAN9252

Note 14: RD_WR and ENB signaling.

Note 15: RD and WR signaling.

Note:

Timing values are with respect to an equivalent test load of 25 pF.

TABLE 9-4:

INDEXED ADDRESSING READ CYCLE TIMING VALUES

Symbol

Description

Min

Typ

Max

Units

tcsrd

CS Setup to RD or ENB Active

trdcs

CS Hold from RD or ENB Inactive

tas

Address Setup to RD or ENB Active

tah

Address Hold from to RD or ENB Inactive

trdwrs

RD_WR Setup to ENB Active

Note 14

5ns

trdwrh

RD_WR Hold from ENB Inactive

Note 14

5ns

trdon

RD or ENB to Data Buffer Turn On

trddv

RD or ENB Active to Data Valid

trddh

Data Output Hold Time from RD or ENB Inactive

trddz

Data Buffer Turn Off Time from RD or ENB Inactive

tcson

CS to Data Buffer Turn On

tcsdv

CS Active to Data Valid

tcsdh

Data Output Hold Time from CS Inactive

tcsdz

Data Buffer Turn Off Time from CS Inactive

tadv

Address to Data Valid

trd

RD or ENB Active Time

trdcyc

RD or ENB Cycle Time

trdrd

RD or ENB De-assertion Time before Next RD or ENB

trdwr

RD De-assertion Time before Next WR

Note 15

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