LAN9252SLASHML datasheet(103/329 Pages) MICROCHIP

103 / 329 page

 2015 Microchip Technology Inc.

DS00001909A-page 103

LAN9252

All instructions, addresses and data are transferred with the most-significant bit (msb) or di-bit (msd) or nibble (msn)

first. Addresses are transferred with the most-significant byte (MSB) first. Data is transferred with the least-significant

byte (LSB) first (little endian).

The SPI interface supports up to a 80 MHz input clock. Normal (non-high speed) reads instructions are limited to 30

MHz.

The SPI interface supports a minimum time of 50 ns between successive commands (a minimum SCS# inactive time of

50 ns).

The instructions supported in SPI mode are listed in Table 10-1. SQI instructions are listed in Table 10-2. Unsupported

instructions are must not be used.

Note 1:

The bit width format is: command bit width, address / dummy bit width, data bit width.

TABLE 10-1:

SPI INSTRUCTIONS

Instruction

Description

Bit width

Note 1

Inst.

code

Addr.

Bytes

Dummy

Bytes

Data

bytes

Max

Freq.

Configuration

EQIO

Enable SQI

1-0-0

38h

80 MHz

RSTQIO

Reset SQI

1-0-0

FFh

80 MHz

Read

READ

Read

1-1-1

03h

4 to



30 MHz

FASTREAD

Read at higher

speed

1-1-1

0Bh

4 to



80 MHz

SDOR

SPI Dual Output

Read

1-1-2

3Bh

4 to



80 MHz

SDIOR

SPI Dual I/O

Read

1-2-2

BBh

4 to



80 MHz

SQOR

SPI Quad Out-

put Read

1-1-4

6Bh

4 to



80 MHz

SQIOR

SPI Quad I/O

Read

1-4-4

EBh

4 to



80 MHz

Write

WRITE

Write

1-1-1

02h

4 to



80 MHz

SDDW

SPI Dual Data

Write

1-1-2

32h

4 to



80 MHz

SDADW

SPI Dual

Address / Data

Write

1-2-2

B2h

4 to



80 MHz

SQDW

SPI Quad Data

Write

1-1-4

62h

4 to



80 MHz

SQADW

SPI Quad

Address / Data

Write

1-4-4

E2h

4 to



80 MHz

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