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LAN9252/ML 数据表(PDF) 104 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 104 Page - Microchip Technology |
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104 / 329 page  LAN9252 DS00001909A-page 104 2015 Microchip Technology Inc. Note 2: The bit width format is: command bit width, address / dummy bit width, data bit width. 10.2.1 DEVICE INITIALIZATION Until the device has been initialized to the point where the various configuration inputs are valid, the SPI/SQI interface does not respond to and is not affected by any external pin activity. Once device initialization completes, the SPI/SQI interface will ignore the pins until a rising edge of SCS# is detected. 10.2.1.1 SPI/SQI Slave Read Polling for Initialization Complete Before device initialization, the SPI/SQI interface will not return valid data. To determine when the SPI/SQI interface is functional, the Byte Order Test Register (BYTE_TEST) should be polled. Once the correct pattern is read, the interface can be considered functional. At this point, the Device Ready (READY) bit in the Hardware Configuration Register (HW_CFG) can be polled to determine when the device is fully configured. 10.2.2 ACCESS DURING AND FOLLOWING POWER MANAGEMENT During any power management mode other than D0, reads and writes are ignored and the SPI/SQI interface does not respond to and is not affected by any external pin activity. Once the power management mode changes back to D0, the SPI/SQI interface will ignore the pins until a rising edge of SCS# is detected. To determine when the SPI/SQI interface is functional, the Byte Order Test Register (BYTE_TEST) should be polled. Once the correct pattern is read, the interface can be considered functional. At this point, the Device Ready (READY) bit in the Hardware Configuration Register (HW_CFG) can be polled to determine when the device is fully configured. 10.2.3 SPI CONFIGURATION COMMANDS 10.2.3.1 Enable SQI The Enable SQI instruction changes the mode of operation to SQI. This instruction is supported in SPI bus protocol only with clock frequencies up to 80 MHz. This instruction is not supported in SQI bus protocol. The SPI slave interface is selected by first bringing SCS# active. The 8-bit EQIO instruction, 38h, is input into the SI/ SIO[0] pin one bit per clock. The SCS# input is brought inactive to conclude the cycle. TABLE 10-2: SQI INSTRUCTIONS Instruction Description Bit width Note 2 Inst. code Addr. Bytes Dummy Bytes Data bytes Max Freq. Configuration RSTQIO Reset SQI 4-0-0 FFh 0 0 0 80 MHz Read FASTREAD Read at higher speed 4-4-4 0Bh 2 3 4 to 80 MHz Write WRITE Write 4-4-4 02h 2 0 4 to 80 MHz Note: The Host should only use single register reads (one data cycle per SCS# low) while polling the BYTE_TEST register. Note: The Host should only use single register reads (one data cycle per SCS# low) while polling the BYTE_TEST register. |
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